公开(公告)号：WO2006099584A2

公开(公告)日：2006-09-21

申请号：PCT/US2006/009782

申请日：2006-03-14

Applicant: QUALCOMM INCORPORATED ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ANDERSON, William C.

Inventor： JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ANDERSON, William C.

IPC: G06F9/38

CPC classification number: G06F9/3851

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The triggering event is variably and dynamically determined to optimize multithreaded processor performance. The triggering event may be a dynamically determined number of processor cycles, the number being determined to optimize the performance of the multithreaded processor, or a variably and dynamically determined event, such as a cache or instruction miss.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 多线程处理器处理通过与多线程处理器相关联的多个处理器管线操作的多个线程，并且预先确定用于多线程处理器从第一线程切换到第二线程的触发事件。 触发事件是可变和动态的，以优化多线程处理器性能。 触发事件可以是动态确定的处理器周期数，被确定为优化多线程处理器的性能的数量，或可变和动态确定的事件，例如高速缓存或指令未命中。

公开(公告)号：WO2017222798A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/036041

申请日：2017-06-06

Applicant: QUALCOMM INCORPORATED

Inventor： MAHURIN, Eric Wayne ,  GOLAB, Jakub Pawal ,  CODRESCU, Lucian

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/00

Abstract: Systems and methods relate to efficient memory operations. A single instruction multiple data (SIMD) gather operation is implemented with a gather result buffer located within or in close proximity to memory, to receive or gather multiple data elements from multiple orthogonal locations in a memory, and once the gather result buffer is complete, the gathered data is transferred to a processor register. A SIMD copy operation is performed by executing two or more instructions for copying multiple data elements from multiple orthogonal source addresses to corresponding multiple destination addresses within the memory, without an intermediate copy to a processor register. Thus, the memory operations are performed in a background mode without direction by the processor.

Abstract translation: 系统和方法涉及有效的存储器操作。 利用位于存储器内或紧邻存储器的收集结果缓冲器来实现单指令多数据（SIMD）收集操作，以从存储器中的多个正交位置接收或收集多个数据元素，并且一旦收集结果缓冲器完成， 收集的数据被传送到处理器寄存器。 SIMD复制操作通过执行两个或更多指令来执行，用于将多个正交源地址的多个数据元素复制到存储器内的相应的多个目的地地址，而不需要中间复制到处理器寄存器。 因此，存储器操作在处理器没有指示的背景模式下执行。

公开(公告)号：WO2016032643A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/041725

申请日：2015-07-23

Applicant: QUALCOMM INCORPORATED

Inventor： VENKUMAHANTI, Suresh Kumar ,  GHIYA, Ankit ,  SASSONE, Peter Gene ,  CODRESCU, Lucian ,  MAMIDI, Suman

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3891

Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.

Abstract translation: 一种方法包括在调度单元处识别可由第一处理集群和第二处理集群访问的共享处理资源处的资源冲突，其中第一处理集群，第二处理集群和共享处理资源是 包括在一个很长的指令字（VLIW）处理单元中。 该方法还包括解决资源冲突。

公开(公告)号：WO2015183462A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/028443

申请日：2015-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZHOU, Bo ,  ZENG, Mao ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  XIAO, Shu ,  DU, Junchen ,  JALIL, Suhail

IPC: H04N19/91 ,  G06F9/30 ,  G06F9/38

CPC classification number: H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

Abstract translation: 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。

公开(公告)号：WO2014159444A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/023708

申请日：2014-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian

IPC: G06F9/48 ,  G06F9/455

CPC classification number: G06F9/4881 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F2009/4557

Abstract: An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a hypervisor to create a virtual processor to execute the requested task. The virtual processor is schedulable on the processor.

Abstract translation: 一种装置包括处理器和客户机操作系统。 响应于接收到创建任务的请求，客户操作系统请求管理程序创建虚拟处理器以执行所请求的任务。 虚拟处理器可在处理器上进行调度。

公开(公告)号：WO2014133784A2

公开(公告)日：2014-09-04

申请号：PCT/US2014/016391

申请日：2014-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： MCDONALD, Michael R. ,  PLONDKE, Erich J. ,  POTOPLYAK, Pavel ,  CODRESCU, Lucian ,  KUO, Richard ,  BAYERDORFFER, Bryan C.

IPC: G06F9/50

CPC classification number: G06F9/3005 ,  G06F9/38 ,  G06F9/4552 ,  G06F9/45537 ,  G06F9/45554 ,  G06F9/45558 ,  G06F9/5044 ,  G06F9/52 ,  G06F2209/509

Abstract: An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on the first processor and the second processor.

Abstract translation: 一种装置包括具有第一指令集的第一处理器和具有与第一指令集不同的第二指令集的第二处理器。 该装置还包括存储操作系统的至少一部分的存储器。 该操作系统可同时在第一处理器和第二处理器上执行。

公开(公告)号：WO2014113286A2

公开(公告)日：2014-07-24

申请号：PCT/US2014/011027

申请日：2014-01-10

Applicant: QUALCOMM INCORPORATED

Inventor： VENKUMAHANTI, Suresh K. ,  PLONDKE, Erich J. ,  CODRESCU, Lucian ,  MAHON, Shane M. ,  TOLEY, Rahul R. ,  HAMDAN, Fadi A.

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.

Abstract translation: 一种装置包括转换后备缓冲器（TLB）。 TLB包括至少一个条目，该条目包括与条目页面对应的条目虚拟地址和条目​​页面大小指示。 该装置还包括输入逻辑，其被配置为接收输入页面大小指示和对应于输入页面的输入虚拟地址。 该设备进一步包括重叠检查逻辑，其被配置为至少部分地基于所述条目页面大小指示和所述输入页面大小指示来确定所述输入页面是否与所述条目页面重叠。

公开(公告)号：WO2013181427A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/043419

申请日：2013-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZENG, Mao ,  PLONDKE, Erich James ,  CODRESCU, Lucian

IPC: G06K9/46

CPC classification number: G06K9/4638

Abstract: A method of determining whether a particular pixel of an image is a feature includes receiving data corresponding to a plurality of pixels (from the image) surrounding the particular pixel. The method further includes determining a set of comparison results, each corresponding to one of the plurality of pixels and indicating a result of comparing an attribute value corresponding to one of the plurality of pixels to a comparison value (based on a particular attribute value of the particular pixel and a threshold value). The method further includes performing a processor-executable instruction that, when executed by a processor, causes the processor to identify a subset of the set of comparison results that indicate the particular pixel is the feature. The identified subset may be a consecutive order of pixels of the plurality of pixels.

Abstract translation: 确定图像的特定像素是否是特征的方法包括接收与围绕该特定像素的多个像素（来自图像）相对应的数据。 所述方法还包括确定一组比较结果，每一个对应于所述多个像素之一并且指示将与所述多个像素中的一个相对应的属性值与比较值（基于所述多个像素的特定属性值）进行比较的结果 特定像素和阈值）。 所述方法还包括执行处理器可执行指令，所述指令在由处理器执行时使所述处理器识别所述特定像素是所述特征的所述一组比较结果的子集。 所识别的子集可以是多个像素的像素的连续顺序。

公开(公告)号：WO2013169836A1

公开(公告)日：2013-11-14

申请号：PCT/US2013/040040

申请日：2013-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： KOOB, Christpher Edward ,  INGLE, Ajay Anant ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh K.

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F12/0848 ,  G06F12/0864

Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache (104) of a multi-threaded processor (102). A memory management unit (110) is configured to determine attributes associated with an address for a cache entry associated with a processing thread (T0) to be allocated in the cache. A configuration register (CP 300_0) is configured to store cache allocation information based on the determined attributes. A partitioning register (DP 310) is configured to store partitioning information for partitioning the cache into two or more portions (Main/Aux in FIG. 3). The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Abstract translation: 用于在多线程处理器（102）的共享分区高速缓存（104）中分配高速缓存行的系统和方法。 存储器管理单元（110）被配置为确定与要在高速缓存中分配的处理线程（T0）相关联的高速缓存条目的地址相关联的属性。 配置寄存器（CP 300_0）被配置为基于所确定的属性来存储高速缓存分配信息。 分区寄存器（DP 310）被配置为存储用于将高速缓存分割成两个或更多个部分（图3中的主/辅助）的分区信息。 基于配置寄存器和分区寄存器，缓存条目被分配到高速缓存的一部分中。

公开(公告)号：WO2013158903A1

公开(公告)日：2013-10-24

申请号：PCT/US2013/037206

申请日：2013-04-18

Applicant: QUALCOMM INCORPORATED

Inventor： ZHOU, Bo ,  ZENG, Mao ,  DU, Junchen ,  CODRESCU, Lucian ,  JALIL, Suhail

IPC: H04N7/26 ,  H04N7/36

CPC classification number: H04N19/523 ,  H04N19/43 ,  H04N19/80

Abstract: A set of even interpolated sub-pixels is formed based on a pixel window and a tap coefficient register having a tap coefficient set, the pixel window is shifted and, applying the tap coefficient register a set of odd interpolated pixels is formed. The set of even interpolated sub-pixels and the set of odd interpolated sub-pixels are accumulated, repeatedly, until a termination condition is let. In the accumulating, the tap coefficient register is updated with another tap coefficient set, the pixel window is shifted, and the even interpolated pixels are incremented, the pixel window is then shifted again and the odd interpolated pixels are incremented.

Abstract translation: 基于像素窗口和具有抽头系数集合的抽头系数寄存器形成一组偶数内插子像素，像素窗口被移位，并且形成抽头系数寄存器一组奇插值像素。 偶数内插子像素组和奇数内插子像素组被重复累积，直到终止条件为let。 在累积中，抽头系数寄存器用另一个抽头系数组更新，像素窗口被移位，并且偶数内插像素递增，然后像素窗口再次移位，并且奇数内插像素增加。