公开(公告)号：EP2659584A1

公开(公告)日：2013-11-06

申请号：EP11815885.6

申请日：2011-12-28

Applicant: Qualcomm Incorporated

Inventor： LI, Guansheng ,  LIU, Li ,  TANG, Yiwu

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1225 ,  H03B5/1256 ,  H03B5/1262 ,  H03B5/1281 ,  H03B5/1296

Abstract: A VCO includes a transformer-based resonator that has a first LC tank and a second LC tank. The resonator has an even resonant mode and an odd resonant mode. The VCO further includes an active transconductance network that is coupled to a two-terminal port of the first tank and is also coupled to a two-terminal port of the second tank. A first terminal of the port of the first tank is capacitively coupled to a first terminal of the port of the second tank. A second terminal of the port of the first tank is capacitively coupled to a second terminal of the port of the second tank. The active transconductance network causes the resonator to resonate in a selectable one of the even and odd resonant modes depending on a digital control signal. The VCO is fine tuned by changing the capacitances of capacitors of the tanks.

公开(公告)号：EP2625783A2

公开(公告)日：2013-08-14

申请号：EP11774137.1

申请日：2011-10-05

Applicant: Qualcomm Incorporated

Inventor： LIU, Li ,  NARATHONG, Chiewcharn

IPC: H03B5/12 ,  H03L1/02

CPC classification number: H03L1/025 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03L1/023 ,  H03L7/099 ,  H03L7/104 ,  H03L7/1976

Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.

公开(公告)号：EP4393065A1

公开(公告)日：2024-07-03

申请号：EP22777796.8

申请日：2022-08-30

Applicant: QUALCOMM INCORPORATED

Inventor： WANG, Chuan ,  LIU, Li ,  ASURI, Bhushan Shanti ,  SAHOTA, Gurkanwal Singh ,  BELLAOUAR, Abdellatif ,  PANIKKATH, Vinod

IPC: H04B1/38 ,  H03F1/02 ,  H03F3/24 ,  H04B1/48 ,  H03F3/72

CPC classification number: H03F2200/45120130101 ,  H03F1/0288 ,  H03F3/72 ,  H03F3/24 ,  H03F2200/53720130101 ,  H03F2200/29420130101 ,  H04B1/38 ,  H04B1/48

公开(公告)号：EP2973998B1

公开(公告)日：2017-05-10

申请号：EP14715750.7

申请日：2014-03-07

Applicant: Qualcomm Incorporated

Inventor： LIU, Li ,  SAMPATH, Praveen-Kumar ,  LEUNG, Lai Kan ,  NARATHONG, Chiewcharn ,  LAU, Soon-Seng ,  HUMNABADKAR, Ketan ,  CHALLA, Raghu Narayan ,  GODBOLE, Devavrata Vasant

IPC: H03D3/00 ,  H03B21/01 ,  H04W52/02

CPC classification number: H04L7/0331 ,  H03B21/01 ,  H03D3/009 ,  H04W52/02 ,  H04W52/0209 ,  Y02D70/1222 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.

Abstract translation: 公开了用于检测和校正本地振荡器（LO）信号的相位不连续性的技术。 在一种设计中，无线设备包括LO发生器和相位检测器。 LO发生器产生用于频率转换的LO信号并周期性地开启和关闭。 当LO发生器通电时，相位检测器检测LO信号的相位。 LO信号的检测到的相位用于识别LO信号的相位不连续性。 该无线设备可以进一步包括（i）产生用于检测LO信号的相位的单音信号的单音产生器，（ii）下变频器，用LO信号下变频单音信号并提供 由相位检测器用于检测LO信号的相位的下变频信号，以及（iii）校正模拟域或数字域中的LO信号的相位不连续性的相位校正器。

公开(公告)号：EP2351208B1

公开(公告)日：2016-09-28

申请号：EP09749276.3

申请日：2009-10-30

Applicant: QUALCOMM Incorporated

Inventor： KHATRI, Himanshu ,  LIU, Li

IPC: H03D7/14

CPC classification number: H03D7/1441 ,  H03D7/1433 ,  H03D7/1466 ,  H03D2200/0043

公开(公告)号：EP2974028A1

公开(公告)日：2016-01-20

申请号：EP14715181.5

申请日：2014-03-11

Applicant: Qualcomm Incorporated

Inventor： LIU, Li ,  NARATHONG, Chiewcharn

IPC: H03L7/18

CPC classification number: H04B1/16 ,  H03L7/099 ,  H03L7/18

Abstract: In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider receives the oscillator signal and generates multiple divided signals of different phases. The PLL receives a reference signal and a selected divided signal and generates the control signal for the oscillator. The divider is powered on and off periodically and wakes up in one of multiple possible states, with each state being associated with a different phase of the selected divided signal. Phase continuity of the selected divided signal is ensured by using the divider as part of the PLL. The PLL locks the selected divided signal to the reference signal, and the selected divided signal has continuous phase due to the reference signal having continuous phase.

公开(公告)号：EP2974020A1

公开(公告)日：2016-01-20

申请号：EP14715182.3

申请日：2014-03-11

Applicant: Qualcomm Incorporated

Inventor： PARK, Dongmin ,  LIU, Li ,  RONG, Sujiang

IPC: H03K5/08 ,  H03K6/02

CPC classification number: H03K5/08 ,  H03K6/02

Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

Abstract translation: 高速电流模式时钟驱动器包括反馈电路，以将偏置节点的电压摆幅保持在限定的范围内。 电流模式时钟驱动器包括在其栅极端子处接收振荡信号的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的漏极端子分别耦合到输出端耦合到公共节点的第一和第二可变电导率电路的输入端。 控制电路响应于公共节点的电压摆幅的减小而增加第一和第二可变电导率电路的电导率，并且响应于公共节点的电压摆幅的增加而降低第一和第二可变电导率电路的电导率。 第一和第二可变电导率电路分别是PMOS和NMOS晶体管。

公开(公告)号：EP2371064B1

公开(公告)日：2015-02-25

申请号：EP09760441.7

申请日：2009-11-25

Applicant: QUALCOMM Incorporated

Inventor： PANIKKATH, Vinod, V. ,  LIU, Li

IPC: H03L7/08 ,  H03K5/156

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03L7/08

公开(公告)号：EP2327152A1

公开(公告)日：2011-06-01

申请号：EP09791629.0

申请日：2009-08-18

Applicant: QUALCOMM Incorporated

Inventor： LIU, Li ,  GUDEM, Prasad, S.

IPC: H03F1/56 ,  H03F3/45

CPC classification number: H03F1/32 ,  H03F1/0277 ,  H03F1/223 ,  H03F1/56 ,  H03F3/45188 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2203/45386 ,  H03F2203/45394 ,  H03F2203/45726 ,  H03F2203/7206 ,  H03F2203/7236 ,  H04B1/109 ,  H04B1/18

Abstract: A receiver includes a low noise amplifier (LNA) and multiple pairs of mixers. The LNA receives and amplifies an LNA input signal and provides at least one LNA output signal. Each pair of mixers downconverts one of the at least one LNA output signal when enabled. Each pair of mixers may be selectively enabled or disabled, e.g., based on a mode selected from among multiple modes. In one design, the LNA includes multiple load sections coupled in parallel. Each load section may be selectively enabled or disabled, e.g., based on the selected mode. In one design, first and second pairs of mixers and first and second load sections may be enabled for a high linearity mode. The first pair of mixers and the first load section may be enabled and the second pair of mixers and the second load section may be disabled for a low linearity mode.

Abstract translation: 接收机包括低噪声放大器（LNA）和多对混频器。 LNA接收并放大LNA输入信号并提供至少一个LNA输出信号。 当使能时，每对混频器下变频至少一个LNA输出信号。 可以例如基于从多个模式中选择的模式来选择性地启用或禁用每对混频器。 在一个设计中，LNA包括并联耦合的多个负载部分。 可以例如基于所选择的模式来选择性地启用或禁用每个加载部分。 在一种设计中，第一和第二对混频器以及第一和第二负载部分可被启用用于高线性模式。 可以启用第一对混频器和第一负载部分，并且可以对于低线性模式禁用第二对混频器和第二负载部分。

公开(公告)号：EP2294699A1

公开(公告)日：2011-03-16

申请号：EP09731682.2

申请日：2009-04-15

Applicant: QUALCOMM Incorporated

Inventor： GUDEM, Prasad, S. ,  CABANILLAS, Jose ,  CHANG, Li-Chung ,  LIU, Li

IPC: H04B1/10

CPC classification number: H04B1/109 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/193 ,  H03F3/245

Abstract: A receiver includes a jammer detector configured to detect the presence or the absence of jamming in a communication signal within a gain state. The receiver further includes an amplifier configured to amplify the communication signal in a high linearity receiving mode or a low linearity receiving mode, wherein the high linearity receiving mode corresponds with a lower gain for the gain state in the amplifier relative to that of the low linearity receiving mode. In addition, the receiver includes a processing unit coupled to the jammer detector, the processing unit being configured to control the amplifier to amplify the communication signal in either the high linearity receiving mode or the low linearity receiving mode, based on the output of the jammer detector detecting the presence or the absence of jamming in the communication signal. A method is also provided for processing a communication signal in a receiver.