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公开(公告)号：WO2023048908A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/041959
申请日：2022-08-30
Applicant: QUALCOMM INCORPORATED
Inventor： WANG, Chuan , LIU, Li , ASURI, Bhushan Shanti , SAHOTA, Gurkanwal Singh , BELLAOUAR, Abdellatif , PANIKKATH, Vinod
Abstract: A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.
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公开(公告)号：WO2012048034A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/054971
申请日：2011-10-05
Applicant: QUALCOMM INCORPORATED , LIU, Li , NARATHONG, Chiewcharn
Inventor： LIU, Li , NARATHONG, Chiewcharn
CPC classification number: H03L1/025 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03L1/023 , H03L7/099 , H03L7/104 , H03L7/1976
Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.
Abstract translation: VCO的谐振器包括与电感并联耦合的微调主变容管电路，辅助变容管电路和粗调电容器组电路。 主变容管电路包括可以单独禁用的多个电路部分。 在每个电路部分内的是一个多路复用电路，该电路把微调控制信号（FTAVCS）或温度补偿控制信号（TCAVCS）中的可选一个提供到电路部分内的变容二极管控制节点上。 如果电路部分被启用，则将FTAVCS提供给控制节点，使得电路部分用于微调。 如果电路部分被禁止，则TCAVCS被提供到控制节点上，使得电路部分被用于对抗作为温度的函数的VCO频率漂移。 TCAVCS的电压如何随温度变化而变化，是数字可编程的。
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公开(公告)号：WO2010022093A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/054214
申请日：2009-08-18
Applicant: QUALCOMM INCORPORATED , LIU, Li , GUDEM, Prasad, S.
Inventor： LIU, Li , GUDEM, Prasad, S.
CPC classification number: H03F1/32 , H03F1/0277 , H03F1/223 , H03F1/56 , H03F3/45188 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2203/45386 , H03F2203/45394 , H03F2203/45726 , H03F2203/7206 , H03F2203/7236 , H04B1/109 , H04B1/18
Abstract: A receiver includes a low noise amplifier (LNA) and multiple pairs of mixers. The LNA receives and amplifies an LNA input signal and provides at least one LNA output signal. Each pair of mixers downconverts one of the at least one LNA output signal when enabled. Each pair of mixers may be selectively enabled or disabled, e.g., based on a mode selected from among multiple modes. In one design, the LNA includes multiple load sections coupled in parallel. Each load section may be selectively enabled or disabled, e.g., based on the selected mode. In one design, first and second pairs of mixers and first and second load sections may be enabled for a high linearity mode. The first pair of mixers and the first load section may be enabled and the second pair of mixers and the second load section may be disabled for a low linearity mode.
Abstract translation: 接收机包括低噪声放大器（LNA）和多对混频器。 LNA接收并放大LNA输入信号并提供至少一个LNA输出信号。 当使能时，每对混频器降低至少一个LNA输出信号之一。 可以例如基于从多个模式中选择的模式来选择性地启用或禁用每对混频器。 在一种设计中，LNA包括并联耦合的多个负载部分。 可以例如基于所选择的模式来选择性地启用或禁用每个加载部分。 在一种设计中，第一和第二对混频器以及第一和第二负载部分可以被启用用于高线性模式。 可以启用第一对混频器和第一负载部分，并且可以对低线性模式禁用第二对混频器和第二负载部分。
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4.发明申请METHOD AND APPARATUS FOR REDUCING INTERMODULATION DISTORTION IN AN ELECTRONIC DEVICE HAVING AN AMPLIFIER CIRCUIT 审中-公开用于减小具有放大器电路的电子设备中的互调失真的方法和装置
公开(公告)号：WO2009097353A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/032272
申请日：2009-01-28
Applicant: QUALCOMM INCORPORATED , DENG, Junxiong , LIU, Li , GUDEM, Prasad, S.
Inventor： DENG, Junxiong , LIU, Li , GUDEM, Prasad, S.
CPC classification number: H03F3/193 , H03F1/223 , H03F1/3205 , H03F1/34 , H03F2200/294 , H03F2201/3206
Abstract: An electronic device includes an amplifier circuit coupled to a linearizer. The amplifier circuit may receive a first input signal including first and second frequencies and generate a first output signal including a delta frequency signal at a delta frequency, which is the difference between the first frequency and the second frequency. The linearizer includes a signal detector circuit, a current-mirror circuit, a low pass filter, a phase shifter, and a bias circuit. The signal detector circuit may generate a second output signal. The current-mirror circuit may adjust an amplitude of a signal. The low pass filter may eliminate a portion of the second output signal having frequencies greater than the delta frequency. The phase shifter may generate a feedback signal corresponding to the delta frequency signal. An amplitude and/or a phase of the feedback signal is different from an amplitude and/or a phase of the delta frequency signal.
Abstract translation: 电子设备包括耦合到线性化器的放大器电路。 放大器电路可以接收包括第一和第二频率的第一输入信号，并产生第一输出信号，该第一输出信号包括第一频率和第二频率之间的差异的增量频率的增量频率信号。 线性化器包括信号检测器电路，电流镜电路，低通滤波器，移相器和偏置电路。 信号检测器电路可以产生第二输出信号。 电流镜电路可以调节信号的幅度。 低通滤波器可以消除具有大于Δ频率的频率的第二输出信号的一部分。 移相器可以产生对应于Δ频率信号的反馈信号。 反馈信号的振幅和/或相位与增量频率信号的振幅和/或相位不同。
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公开(公告)号：WO2009026413A1
公开(公告)日：2009-02-26
申请号：PCT/US2008/073812
申请日：2008-08-21
Applicant: QUALCOMM Incorporated , LIU, Li , GUDEM, Prasad S.
Inventor： LIU, Li , GUDEM, Prasad S.
CPC classification number: H04B1/109 , H03F1/223 , H03F1/3205 , H03F1/3211 , H03F3/45179 , H03F3/45188 , H03F2200/453 , H03F2203/45306 , H03F2203/45352 , H03F2203/45386 , H03F2203/45394 , H04B1/525
Abstract: Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.
Abstract translation: 描述了通过失真消除线性化的有源负载的有源电路。 在一种设计中，装置包括第一级和负载级。 对于放大器，第一级放大输入信号并提供具有较大信号电平的输出信号。 对于混频器，第一级将输入信号与LO信号混频并提供输出信号。 负载级为第一级提供有效负载，并通过消除由有效负载产生的失真来线性化。 在一种设计中，负载级包括提供有源负载并由于其非线性而产生失真的第一晶体管。 负载级还包括至少一个晶体管，其产生来自第一晶体管的失真的复制品。 失真复制品用于消除第一晶体管的失真。 第一级也可以通过失真消除线性化。
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Patent Agency Ranking
公开(公告)号：WO2023038792A1
公开(公告)日：2023-03-16
申请号：PCT/US2022/041205
申请日：2022-08-23
Applicant: QUALCOMM INCORPORATED
Inventor： ABOUZIED, Mohamed , PANIKKATH, Vinod , LIU, Li , WANG, Chuan
IPC: G01R21/01
Abstract: An aspect relates to an apparatus including a radio frequency (RF) signal power detector. The RF signal power detector includes a first current source configured to generate a first current based on a power level of a first RF signal; a transimpedance amplifier (TIA) configured to generate a first voltage based on the first current, wherein the TIA is coupled between a first upper voltage rail and a lower voltage rail; and a second current source configured to generate a second current related to the first current, wherein the first and second current sources are coupled in series between a second upper voltage rail and the lower voltage rail.
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公开(公告)号：WO2023034002A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/040079
申请日：2022-08-11
Applicant: QUALCOMM INCORPORATED
Inventor： WANG, Chuan , ASURI, Bhushan Shanti , LIU, Li , PANIKKATH, Vinod
Abstract: In certain aspects, a method includes receiving a first intermediate frequency (IF) signal and a second IF signal via a common input, upconverting the first IF signal into a first radio frequency (RF) signal, transmitting the first RF signal via a first antenna array, upconverting the second IF signal into a second RF signal, and transmitting the second RF signal via a second antenna array. In a first transit mode, the first RF signal is in a first frequency band and the second RF signal is in a second frequency band, and, in a second transmit mode, the first RF signal and the second RF signal are both in the first frequency band.
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公开(公告)号：WO2020236801A1
公开(公告)日：2020-11-26
申请号：PCT/US2020/033576
申请日：2020-05-19
Applicant: QUALCOMM INCORPORATED
Inventor： PATEL, Chirag Dipak , GOLDBLATT, Jeremy , FENG, Yunfei , LIU, Li , YU, Xinmin , HOMAYOUN, Aliakbar
Abstract: An apparatus is disclosed for mixing signals with a multi-mode mixer for frequency translation. In example implementations, a multi-mode mixer includes a supply voltage node, a ground node, a first data signal coupler, and a second data signal coupler. The multi-mode mixer also includes a mixer core and a current control switch. The mixer core is coupled between the first data signal coupler and the second data signal coupler. The current control switch is configured to selectively enable or disable flow of a current through the mixer core. The first data signal coupler, the second data signal coupler, the mixer core, and the current control switch are coupled together in series between the supply voltage node and the ground node.
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公开(公告)号：WO2020068634A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/052377
申请日：2019-09-23
Applicant: QUALCOMM INCORPORATED
Inventor： LIU, Li , WANG, Kevin Hsi Huai , FENG, Yunfei , WANG, Chuan , SAHOTA, Gurkanwal
IPC: H04B7/0408 , H04B7/06 , H04B7/08 , H01Q23/00 , H04B1/00 , H04B7/0404
Abstract: An apparatus is disclosed for a hybrid wireless transceiver architecture that supports multiple antenna arrays. In an example aspect, the apparatus includes a first antenna array, a second antenna array, and a wireless transceiver. The wireless transceiver includes first dedicated circuitry dedicated to the first antenna array and second dedicated circuitry dedicated to the second antenna array. The wireless transceiver also includes shared circuitry that is shared with both the first antenna array and the second antenna array.
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10.发明申请LOCAL OSCILLATOR (LO) GENERATOR WITH MULTI-PHASE DIVIDER AND PHASE LOCKED LOOP 审中-公开具有多相分离器和相位锁定环路的本地振荡器（LO）发生器
公开(公告)号：WO2014150575A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/023667
申请日：2014-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： LIU, Li , NARATHONG, Chiewcharn
IPC: H03L7/18
Abstract: In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider receives the oscillator signal and generates multiple divided signals of different phases. The PLL receives a reference signal and a selected divided signal and generates the control signal for the oscillator. The divider is powered on and off periodically and wakes up in one of multiple possible states, with each state being associated with a different phase of the selected divided signal. Phase continuity of the selected divided signal is ensured by using the divider as part of the PLL. The PLL locks the selected divided signal to the reference signal, and the selected divided signal has continuous phase due to the reference signal having continuous phase.
Abstract translation: 在一种设计中，装置包括振荡器，分频器和锁相环（PLL）。 振荡器接收控制信号并提供具有由控制信号确定的频率的振荡器信号。 分频器接收振荡器信号并产生不同相位的多个分频信号。 PLL接收参考信号和选择的分频信号，并产生振荡器的控制信号。 分频器周期性地通电和关断，并在多个可能状态之一中唤醒，每个状态与所选分频信号的不同相位相关联。 通过使用分频器作为PLL的一部分来确保所选分频信号的相位连续性。 PLL将所选择的分频信号锁定到参考信号，并且由于具有连续相位的参考信号，所选择的分频信号具有连续相位。
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