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    Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
    56.
    发明授权
    Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC) 有权
    多通道模数转换器（ADC）中车道不平衡的补偿

    公开(公告)号：US09030341B2

    公开(公告)日：2015-05-12

    申请号：US13553017

    申请日：2012-07-19

    Applicant: Loke Tan ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

    Inventor： Loke Tan ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

    IPC: H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/1052 ,  H03M1/1215

    Abstract: Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

    Abstract translation: 公开了各种多通道ADC，其基本上补偿由各种损伤（例如相位偏移，幅度偏移和/或DC偏移）导致的各种信号内存在的损伤，以提供一些示例，使得它们各自的数字输出样本准确地表示它们 各自的模拟输入。 通常，各种多通道ADC确定各种统计关系，例如各种相关性，以提供这些各种信号之间的示例，以及各种已知的校准信号，以量化可能存在的相位偏移，幅度偏移和/或DC偏移 各种信号。 各种多通道ADC基于这些各种统计关系调整各种信号以基本上补偿相位偏移，幅度偏移和/或DC偏移，使得它们各自的数字输出样本精确地表示它们各自的模拟输入。

    Successive equalizer for analog-to-digital converter (ADC) error correction
    57.
    发明授权
    Successive equalizer for analog-to-digital converter (ADC) error correction 有权
    用于模数转换器（ADC）误差校正的连续均衡器

    公开(公告)号：US08717209B2

    公开(公告)日：2014-05-06

    申请号：US13604184

    申请日：2012-09-05

    Applicant: Jiangfeng Wu ,  Tianwei Li ,  Wenbo Liu ,  Wei-Ta Shih ,  Chun-Ying Chen ,  Lin He ,  Randall Perlow ,  Binning Chen ,  Ramon Gomez

    Inventor： Jiangfeng Wu ,  Tianwei Li ,  Wenbo Liu ,  Wei-Ta Shih ,  Chun-Ying Chen ,  Lin He ,  Randall Perlow ,  Binning Chen ,  Ramon Gomez

    IPC: H03M1/06

    CPC classification number: H03M1/0626 ,  H03M1/0614 ,  H03M1/44

    Abstract: Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

    Abstract translation: 公开了各种流水线ADC，其基本上补偿由流水线ADC的各种ADC模块的缺陷导致的干扰或失真。 流水线ADC包括各种ADC级以及耦合到各个ADC级的各种补偿级。 各个ADC级将其相应的模拟输入从模拟信号域转换为数字信号域，以向后续ADC级提供各种数字输出信号和各种模拟残留信号。 各种补偿级补偿由于先前ADC阶段的缺陷而导致的各种模拟残差信号的干扰或失真。

    Programmable Gain Attenuator With A Wide Attenuation Range And A Fine Attenuation Step Size
    58.
    发明申请
    Programmable Gain Attenuator With A Wide Attenuation Range And A Fine Attenuation Step Size 有权
    可编程增益衰减器，具有宽的衰减范围和精细的衰减步长

    公开(公告)号：US20110140812A1

    公开(公告)日：2011-06-16

    申请号：US12689549

    申请日：2010-01-19

    Applicant: Tao WU ,  Ramon Gomez

    Inventor： Tao WU ,  Ramon Gomez

    IPC: H01P1/22

    CPC classification number: H03H7/25 ,  H03G1/0088 ,  H03G3/001

    Abstract: A programmable gain attenuator (PGA) configured to receive a signal at an input and provide an attenuated version of the signal at an output is provided herein. The PGA includes a resistor coupled between a first tap and a second tap, where the first tap is coupled to the input of the PGA. The PGA further includes two sets of switches. The first set of switches is coupled in parallel between the first tap and the output, and the second set of switches is coupled in parallel between the second tap and the output. The attenuation setting of the programmable gain attenuator can be determined by controlling each set of switches.

    Abstract translation: 一种可编程增益衰减器（PGA），被配置为在输入处接收信号并在输出端提供信号的衰减版本。 PGA包括耦合在第一抽头和第二抽头之间的电阻器，其中第一抽头耦合到PGA的输入端。 PGA还包括两套开关。 第一组开关并联在第一抽头和输出之间，第二组开关并联在第二抽头和输出端之间。 可编程增益衰减器的衰减设置可以通过控制每组开关来确定。

    Imbalance and distortion cancellation for composite analog to digital converter (ADC)
    59.
    发明申请
    Imbalance and distortion cancellation for composite analog to digital converter (ADC) 有权

    公开(公告)号：US20110063148A1

    公开(公告)日：2011-03-17

    申请号：US12949752

    申请日：2010-11-18

    Applicant: Thomas J. Kolze ,  Bruce J. Currivan ,  Ramon Gomez ,  Loke Tan ,  Lin He

    Inventor： Thomas J. Kolze ,  Bruce J. Currivan ,  Ramon Gomez ,  Loke Tan ,  Lin He

    IPC: H03M1/06 ,  H03M1/50

    CPC classification number: H03M1/1033 ,  H03M1/188

    Abstract: Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs.

    Implementing Continuous Descent Approaches for Maximum Predictability in Aircraft
    60.
    发明申请
    Implementing Continuous Descent Approaches for Maximum Predictability in Aircraft 有权
    实现飞机最大可预测性的连续下降方法

    公开(公告)号：US20100318244A1

    公开(公告)日：2010-12-16

    申请号：US12526099

    申请日：2008-02-22

    Applicant: Ramon Gomez ,  Francisco A. Navarro ,  Bastian Figlar

    Inventor： Ramon Gomez ,  Francisco A. Navarro ,  Bastian Figlar

    IPC: G08G5/02

    CPC classification number: G01C21/00 ,  G08G5/0021 ,  G08G5/0082 ,  G08G5/025 ,  Y02T50/84

    Abstract: The present disclosure relates to methods of calculating and flying continuous descent approaches to an airport or the like, and to aircraft navigation systems for implementing these methods. The present disclosure resides in the recognition that greater predictability in arrival times may be achieved by flying continuous descent approaches by maintaining a constant aerodynamic flight path angle.

    Abstract translation: 本公开涉及计算和飞行连续下降方法到机场等的方法以及用于实施这些方法的飞行器导航系统。 本公开内容在于认识到，通过维持恒定的空气动力学飞行路径角度可以通过飞行连续下降方法来实现到达时间的更大可预测性。

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