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    Treatment of semiconductor wafer
    51.
    发明专利
    Treatment of semiconductor wafer 失效
    半导体晶体管的处理

    公开(公告)号：JPS57117246A

    公开(公告)日：1982-07-21

    申请号：JP344081

    申请日：1981-01-13

    Applicant: Sony Corp

    Inventor： NISHIYAMA KAZUO ,  ARAI MICHIO

    IPC: H01L21/26 ,  H01L21/265 ,  H01L21/324

    CPC classification number: H01L21/324

    Abstract: PURPOSE:To perform necessary treatment suppressing dispersion of impurity, by a high speed treatment, irradiating semiconductor wafer on both sides suspended inside a heating furnace with high power rays. CONSTITUTION:A semiconductor wafer 1 to be heat treated is suspended exposing both main surfaces A and B via a susceptor 6 in a quartz tube 2 to which N2 gas is supplied at the time of the heat treatment. The wafer 1 is irradiated on the both sides 1A, 1B with rays from a tungsten lamp or a halogen lamp 4. Supporting members 3 of lamps are movable in relation to each other. Ion implanted region is electrically activated in a short time without redistributing the ion implanted impurity.

    Abstract translation: 目的：为了进行必要的处理，抑制杂质的分散，通过高速处理，用高功率射线照射放置在加热炉内的两侧的半导体晶片。 构成：将待热处理的半导体晶片1通过在热处理时供给N2气的石英管2中的基座6暴露于主表面A和B两者。 晶片1通过来自钨灯或卤素灯4的光线照射在两侧1A，1B上。灯的支撑构件3可相对于彼此移动。 离子注入区域在短时间内被电活化，而不会重新分布离子注入的杂质。

    SEMICONDUCTOR DEVICE
    52.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS56153784A

    公开(公告)日：1981-11-27

    申请号：JP5268881

    申请日：1981-04-08

    Applicant: SONY CORP

    Inventor： ARAI MICHIO

    IPC: H01L31/10 ,  H01L31/11

    Abstract: PURPOSE:To amplify gate currents sharply by a method wherein a region, a conduction type thereof differs from that of a gate region of a photo-FET, is formed to the gate region thereof, and a trnsistor is formed using the region as an emitter. CONSTITUTION:A P type semiconductor region 13 is built up on a lower surface of an N type semiconductor region 12. A P type semiconductor region 14 functioning as a gate region is formed on the region 12, and an N channel 15 is formed on the region 12 between the region 14 and the region 13. N type semiconductor regions 16, 17 functioning as source and drain regions are built up on the region 12 at the both sides of the region 14. An N type region 18 is formed to the region 14, and a transistor Tr19 is formed between each of the region 18 and the regions 14, 12. In this case, a distance between the region 18 and the channel 15 is designed so as to become smaller than the diffusion distances of electrons injected to the region 19. Thus, photo-currents flowing through a photodiode built up by the regions 18, 14 are sharply amplified by means of the Tr19.

    MANUFACTURE OF SEMICONDUCTOR DEVICE
    53.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS56100412A

    公开(公告)日：1981-08-12

    申请号：JP16374679

    申请日：1979-12-17

    Applicant: SONY CORP

    Inventor： NISHIYAMA KAZUO ,  YANADA TETSUNOSUKE ,  ARAI MICHIO

    IPC: H01L21/26 ,  H01L21/00 ,  H01L21/265 ,  H01L21/268 ,  H05B3/00

    Abstract: PURPOSE:To shorten a time for annealing to a large extent by injecting ions to the surface of a substrate and later applying infrared lamp rays thereto for activation thereof. CONSTITUTION:A wafer 1 after injection of ions is mounted on a board 2 and moved. Infrared rays 4 having wavelength of about 0.4-4mum are emitted from an infrared lamp and reflected by a reflecting mirror 5 having an elliptic curved surface so as to make a spot on the wafer 1 for heating. While the wafer being heated, the board 2 is moved and scanning is made on the wafer. Spot heating with a diameter of 3-5mm. (about 1,000 deg.C) is available. Or the wafer 1 is mounted on a supporting board 7 inside a quartz tube 6, paraboloidal reflecting mirrors 8 are arranged on the upper and lower outsides of the tube 6, and irradiation is made uniformly by the infrared lamps 3. A plurality of pairs may be provided in continuity. By this constitution, the activation of the layer wherein ions are injected is made possible in a short time of 1/10-1/100 of that in the usual case of employment of an electric furnace, and uniform annealing with low energy is enabled, while the unevenness of the activation can be held down to 1% or less.

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