公开(公告)号：JPS5926131B2

公开(公告)日：1984-06-25

申请号：JP7342176

申请日：1976-06-22

Applicant: Sony Corp

Inventor： SOMENO NOBORU ,  MURATA NORIO ,  OOHAMA SOICHI

IPC: H04B1/40 ,  H03J5/02 ,  H03J7/28 ,  H03L7/18 ,  H04B1/26

CPC classification number: H04B1/26 ,  H03J5/0281 ,  H03J7/285

公开(公告)号：JPS57179978A

公开(公告)日：1982-11-05

申请号：JP6538081

申请日：1981-04-30

Applicant: SONY CORP

Inventor： SOMENO NOBORU

IPC: G11B27/28 ,  G11B5/09 ,  G11B15/087 ,  G11B27/30

Abstract: PURPOSE:To quickly and accurately record a control signal at an absolute address, by automatically recording the control signal at the absolute address indicating an audio signal, on a non-recording part. CONSTITUTION:Through the start of a control signal C write operation mode, the tape rewinding operation mode is obtained, a tape end of a magnetic tape 1 is detected, the recording mode is set and the signal C in an absolute address indicating the signal C is recorded. After the end of recording, the reproducing tape fast feed operating mode is set, and the beginning of the 2nd recording A2 located next to the 1st audio signal recording A1 is detected, the reproduction tape rewinding operation mode is set and the end of the recording A1 is detected. Simultaneously, the recording mode is set and the operation recording the signal C of the absolute address indicating the 2nd audio signal is sequentially repeated. The signal C of the absolute address indicating the audio signal is recorded on non-recording parts Z1-Zn formed between a plurality of audio signal recordings.

公开(公告)号：JPS56117180A

公开(公告)日：1981-09-14

申请号：JP1985880

申请日：1980-02-20

Applicant: SONY CORP

Inventor： MUNAKATA KATSUSUKE ,  FURUNO HIROSHI ,  SOMENO NOBORU

IPC: G04G15/00 ,  G04G99/00

Abstract: PURPOSE:To simplify the setting of operational time of a timer by arraying the 1st to 12th switches on the positions of 1-12 oclock on the same circumference and by combining these switches together with a mode switching procedure and a timer circuit. CONSTITUTION:Switches S1-S12 are arrayed on the positions of 1-12 o'clocks on the same circumference and display procedure DP of the output mode is also installed, these are driven by a driving circuit including clock circuit 1, timer circuit 3, coincidence circuit 4, display circuit 7, and input circuit 8 for switches S1-S12 connected like a matrix. When any one of switches S1-S12 is depressed, ''hour'' or ''minute'' corresponding to the position is stored timr circuit 3 and the output is generated at the corresponding time. Thus, the operational time of the timer can be set only by depressing switches S1-S12, making it possible to simplify the operation extremely.

公开(公告)号：JPS5596723A

公开(公告)日：1980-07-23

申请号：JP464679

申请日：1979-01-18

Applicant: SONY CORP

Inventor： SOMENO NOBORU ,  KOMATSUBARA MICHIMASA ,  TOYOSHIMA MASAKATSU

IPC: H03J7/28 ,  H04B1/26

Abstract: PURPOSE:To prevent tuning to the side band of a short duration by delaying pulses which change a receiving state detection FF. CONSTITUTION:When up switch Su is turned on, the count value of counter 31 is increased for every pulse P32, and receiving frequency fi is increased by steps of 9kHz. When scan advances and the receiving frequency becomes (fi-9kHz) to detect the side band of broadcast of frequency fi, output Q37 of detection circuit 37 is changed, however, output Q37 continues hardly to be 1 during delayed output pulse P55 of pulse forming circuit 55 because of a short duration of output Q37 of 1, and output Q54 of AND circuit 54 cannot be changed.

公开(公告)号：JPS5593330A

公开(公告)日：1980-07-15

申请号：JP196379

申请日：1979-01-09

Applicant: SONY CORP

Inventor： SOMENO NOBORU

IPC: H03J7/28 ,  H03J1/02 ,  H04B1/16 ,  H04B1/26

Abstract: PURPOSE:To enable to confirm the channel selection operation with sound, by frequency-dividing the oscillation signal of the oscillation circuit for reference and by obtaining the reproduced sound through the supply of frequency dividing signal to the low frequency part related to this operation. CONSTITUTION:The frequency division signal Sd from the frequency division circuit 42 is fed to the frequency division circuit 61 performing 1/4 frequency division and divided into the signal Sa. When either of the switches Su, Sd, S1- S8 is ON, since the output of the AND circuit 76 is zero, the multi-vibrator 77 is triggered to form the pulse Pm and it is fed to the AND circuit 74. Further, during the period of Pm=''1'', since the signal Sa is fed to the amplifier 32 through the AND circuit 74 and OR circuit 75, the sound of signal Sa is reproduced from the speaker 33 for a short time and the operation of the switch can be confirmed with this reproduction sound.

公开(公告)号：JPS5588436A

公开(公告)日：1980-07-04

申请号：JP16354078

申请日：1978-12-25

Applicant: SONY CORP

Inventor： NISHIMURA YOSHINORI ,  NAKAMURA HIDEO ,  NOJIRI TOSHIHIKO ,  IWASE KOUICHI ,  SOMENO NOBORU

IPC: H03J7/28 ,  H03J5/02 ,  H04B1/16 ,  H04B1/26

Abstract: PURPOSE:To always secure the automatic and continuous reception only for the optimum broadcast by securing the automatic selection for the next channel in case the reception level is lowered for a certain channel under the reception. CONSTITUTION:The IF signal sent from IF amplifier 15 is detected 51 and then supplied to shaping circuit 52, and then the signal which becomes ''1'' and ''0'' when the broadcast reception level is higher and lower than the fixed level respectively is extracted to be supplied to fall trigger type monostable multivibrator 53. The output of vibrator 53 is sent to gate circuit 64, and the output of circuit 52 changes from ''1'' to ''0'' when the level of reception channel becomes lower than the fixed value. Then the output of logic circuit 63 is sent to the input port of interface circuit 34 through circuit 64. As a result, the next channel is selected automatically, thus ensuring the automatic and continuous reception at all times for only the optimum broadcast.

公开(公告)号：JPS54131808A

公开(公告)日：1979-10-13

申请号：JP3962178

申请日：1978-04-03

Applicant: SHARP KK ,  SONY CORP

Inventor： MAEDA HIDETOSHI ,  INOUE KAZUO ,  SOMENO NOBORU

IPC: H03J7/18 ,  G01R23/10 ,  H03J1/00 ,  H03J1/04 ,  H03J3/14 ,  H04B1/16

Abstract: PURPOSE:To realize the counting of the frequency over the entire frequency band in an extremely high accuracy by securing the relation between the program and the frequency band switching mechanism of the reception frequency via the microcomputer and then multiplying the correction coefficient via the arithmetic function. CONSTITUTION:RAM5 is used as the operational register, and ROM6 is used for memorization of the program. And the step is progressed by the clock signal. Here the gate circuit is opened and closed by the program order of ROM6; the input frequency passed through the gate circuit is counted through counter 9; and the value relating the contents of counter 9 is digital-displayed. In this way, the program is correlated with the frequency band switching mechanism of the reception frequency with the correction coefficient multiplied through the arithmetic function, thus ensuring the frequency counting over the entire frequency band in an extremely high accuracy.