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公开(公告)号：US09202002B2
公开(公告)日：2015-12-01
申请号：US14511014
申请日：2014-10-09
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50 , H04L12/933 , G06F15/78 , H04L12/935
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
Abstract translation: 一种用于设计片上网络互连装置的系统包括具有多个骨干端口的片上网络骨干网以及提供各组片上系统功能的聚合IP功能集群的集合。 功能集群包括可连接到任何骨干端口的各个子网络，以及独立于片上网络骨干网骨源的源地图的功能集群中的任何其他功能集群。
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公开(公告)号：US09178776B2
公开(公告)日：2015-11-03
申请号：US13789445
申请日：2013-03-07
Inventor： Ignazio Antonino Urzi , Rene Peyrard , Daniele Mangano
IPC: H04L12/28 , G01R31/08 , H04L12/24 , H04L12/26 , H04L12/815 , H04L12/813 , H04L12/853
CPC classification number: H04L41/5038 , H04L41/0896 , H04L41/5025 , H04L43/0882 , H04L47/20 , H04L47/22 , H04L47/2416
Abstract: A method includes providing at least one target bandwidth for bandwidth usage on an interconnect, the target bandwidth being for traffic associated with a traffic initiator. The method also includes measuring a served bandwidth and resetting the measuring of served bandwidth in response to an occurrence of an event.
Abstract translation: 一种方法包括为互连上的带宽使用提供至少一个目标带宽，所述目标带宽用于与业务发起者相关联的流量。 该方法还包括测量服务带宽并且响应于事件的发生重置服务带宽的测量。
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53.发明授权Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer 有权用于排序乱序数据的缓冲器，以及用于管理缓冲器的相应集成电路和方法公开(公告)号：US09093133B2
公开(公告)日：2015-07-28
申请号：US14143383
申请日：2013-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Marco Rosselli , Giuseppe Falconeri
CPC classification number: G11C7/1006 , G06F5/10 , G06F2205/106 , G06F2205/123
Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.
Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。
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公开(公告)号：US20150033821A1
公开(公告)日：2015-02-05
申请号：US14444920
申请日：2014-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano
IPC: G01C25/00
CPC classification number: G01C25/005 , G01C19/00 , G01C21/10 , G01C21/12 , G01C21/16 , G01C21/18 , G01C25/00 , G01P21/00
Abstract: A method for real-time calibration of a gyroscope, configured for supplying a value of angular velocity that is function of a first angle of rotation about a first angular-sensing axis that includes defining a time interval, acquiring from an accelerometer an equivalent value of angular velocity that can be associated to the first angle of rotation; calculating a deviation between the value of angular velocity and the equivalent value of angular velocity; iteratively repeating the previous steps through the time interval, incrementing or decrementing an offset variable by a first predefined value on the basis of the values assumed by the deviations during the iterations, and updating the value of angular velocity as a function of the offset variable.
Abstract translation: 一种用于陀螺仪的实时校准的方法，其被配置为提供围绕第一角度感测轴线的第一旋转角函数的角速度值，所述第一角度感测轴线包括限定时间间隔，从加速度计获取等效值 可以与第一旋转角度相关联的角速度; 计算角速度值和角速度等效值之间的偏差; 在所述时间间隔内迭代地重复前述步骤，基于由迭代期间的偏差假设的值，将偏移变量递增或递减第一预定义值，以及作为偏移变量的函数更新角速度的值。
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公开(公告)号：US11906995B2
公开(公告)日：2024-02-20
申请号：US17836417
申请日：2022-06-09
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Francesco Clerici , Pasquale Butta'
Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
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Patent Agency Ranking
公开(公告)号：US11803226B2
公开(公告)日：2023-10-31
申请号：US16874020
申请日：2020-05-14
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Michele Alessandro Carrano , Pasquale Butta′ , Sergio Abenda
IPC: G06F1/3234 , H03K3/037 , G06F1/3296
CPC classification number: G06F1/325 , G06F1/3243 , H03K3/037
Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
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公开(公告)号：US11703897B2
公开(公告)日：2023-07-18
申请号：US16810639
申请日：2020-03-05
Inventor： Michel Cuenca , Bruno Gailhard , Daniele Mangano
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.
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公开(公告)号：US20230087239A1
公开(公告)日：2023-03-23
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11496170B2
公开(公告)日：2022-11-08
申请号：US17180751
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
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公开(公告)号：US10788870B2
公开(公告)日：2020-09-29
申请号：US16405086
申请日：2019-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Gaetano Di Stefano , Mirko Dondini
IPC: G06F1/24 , G06F11/267 , H03K3/037
Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
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