公开(公告)号：EP0953984A1

公开(公告)日：1999-11-03

申请号：EP98830265.9

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: G11C16/00 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/105 ,  G11C5/143 ,  G11C16/102

Abstract: Upon unwanted interruption of programming, the control logic unit (2) of the memory (1) controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location (39). To this end, the backup memory location (39) is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators (61) are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory (1) is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.

Abstract translation: 当编程的不想要的中断时，控制逻辑单元（2）的存储器（1）控制所述数据的写入也否则将丢失和其地址，在适当的备份存储位置（39）。 为此，备份存储位置（39）被保持擦除,:如以允许数据和它的地址的直接写入，在编程的中断的情况下。 为了保证即使在没有外部电源的功能，合适的充电电池（61）被提供，从而可以保证只写周期的可用性。 只要检测到的电压降，在正在进行的操作被中断，并且被编程被激活的数据的备份操作; 当内存（1）再次接通，则确认是否中断写入周期已经发生之前，从而和保存的数据可以恢复到主存储器。

公开(公告)号：EP0926737A3

公开(公告)日：1999-07-14

申请号：EP98123137.6

申请日：1998-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Sourgen, Laurent c/o STMicroelctronics S.A. ,  Zatelli, Nicola STMicroelectronics Srl ,  Lisart, Mathieu c/o STMicroelectronics S.A.

IPC: H01L23/58 ,  H01L23/556

CPC classification number: H01L27/115 ,  H01L27/02

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract translation: EEPROM单元被描述为具有在第一金属层中优选形成的屏蔽金属结构，并且在浮置栅极端处以基本上重叠的关系定位。 这就可以通过测量浮置栅极端上的电荷量来获得异常读数的可能性。 可以提供待在第三层和随后的金属层中形成的附加的屏蔽金属结构，以完全覆盖电池，并提供额外的防止异常读数的保护。

公开(公告)号：EP0926737A2

公开(公告)日：1999-06-30

申请号：EP98123137.6

申请日：1998-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Sourgen, Laurent c/o STMicroelctronics S.A. ,  Zatelli, Nicola STMicroelectronics Srl ,  Lisart, Mathieu c/o STMicroelectronics S.A.

IPC: H01L23/58 ,  H01L23/556

CPC classification number: H01L27/115 ,  H01L27/02

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract translation: EEPROM单元被描述为具有筛选金属结构（50），优选地在第一金属层中形成并且在浮动栅极端子（30）处基本上覆盖关系。 这样可以通过测量浮栅端子上的电荷量来获得异常读数的可能性。 可以提供要在第三和随后的金属层中形成的另外的筛选金属结构，以完全覆盖电池并提供额外的防止异常读数的保护。