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    Methods and Apparatus for Velocity Detection in MIMO Radar Including Velocity Ambiguity Resolution
    52.
    发明申请
    Methods and Apparatus for Velocity Detection in MIMO Radar Including Velocity Ambiguity Resolution 审中-公开

    公开(公告)号：US20200209352A1

    公开(公告)日：2020-07-02

    申请号：US16814531

    申请日：2020-03-10

    Applicant: Texas Instruments Incorporated

    Inventor： Sandeep Rao ,  Karthik Subburaj ,  Dan Wang ,  Adeel Ahmad

    IPC: G01S7/35 ,  G01S13/42 ,  G01S13/92 ,  G01S13/34

    Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

    Frequency synthesizer output cycle counter including ring encoder
    53.
    发明授权
    Frequency synthesizer output cycle counter including ring encoder 有权

    公开(公告)号：US10481187B2

    公开(公告)日：2019-11-19

    申请号：US14588014

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Tom Altus ,  Karthik Subburaj ,  Sreekiran Samala ,  Raghu Ganesan

    IPC: G01R23/02 ,  G01R23/10 ,  H03L7/091

    Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.

    Timing for IC chip
    55.
    发明授权
    Timing for IC chip 有权

    公开(公告)号：US10142095B2

    公开(公告)日：2018-11-27

    申请号：US15334979

    申请日：2016-10-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jasbir Singh Nayyar ,  Brian Ginsburg ,  Karthik Subburaj

    IPC: H04L7/00 ,  H01Q1/22

    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

    Synchronization in FMCW Radar Systems
    57.
    发明申请
    Synchronization in FMCW Radar Systems 审中-公开

    公开(公告)号：US20170299693A1

    公开(公告)日：2017-10-19

    申请号：US15635659

    申请日：2017-06-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Karthik Ramasubramanian ,  Karthik Subburaj ,  Sachin Bhardwaj

    IPC: G01S7/35 ,  G01S13/58

    CPC classification number: G01S7/35 ,  G01S13/343 ,  G01S13/584 ,  G01S13/726 ,  G01S13/931 ,  G01S2013/0245

    Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of the plurality of obstacles. The radar apparatus includes a local oscillator that generates a first signal. A first transmit unit receives the first signal from the local oscillator and generates a first transmit signal. A frequency shifter receives the first signal from the local oscillator and generates a second signal. A second transmit unit receives the second signal and generates a second transmit signal. The frequency shifter provides a frequency offset to the first signal based on a routing delay mismatch to generate the second signal such that the first transmit signal is phase coherent with the second transmit signal.

    Linear approximation of a complex number magnitude
    60.
    发明授权
    Linear approximation of a complex number magnitude 有权

    公开(公告)号：US12260187B2

    公开(公告)日：2025-03-25

    申请号：US17357919

    申请日：2021-06-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Joshi ,  Karthik Subburaj ,  Karthik Ramasubramanian

    IPC: G06F7/48 ,  G06F17/14 ,  H03K5/24

    Abstract: A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

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