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    ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCE
    52.
    发明申请
    ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCE 有权

    公开(公告)号：US20230055211A1

    公开(公告)日：2023-02-23

    申请号：US17406150

    申请日：2021-08-19

    Applicant: Texas Instruments Incorporated

    Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

    IPC: H01L23/498 ,  H01L21/48

    Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

    SHAPED INTERCONNECT BUMPS IN SEMICONDUCTOR DEVICES
    53.
    发明申请
    SHAPED INTERCONNECT BUMPS IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230012200A1

    公开(公告)日：2023-01-12

    申请号：US17944143

    申请日：2022-09-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sreenivasan K. Koduri

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56

    Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

    Shaped interconnect bumps in semiconductor devices
    54.
    发明授权
    Shaped interconnect bumps in semiconductor devices 有权

    公开(公告)号：US11444048B2

    公开(公告)日：2022-09-13

    申请号：US16103839

    申请日：2018-08-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sreenivasan K. Koduri

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

    Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

    PACKAGE FOR POWER SEMICONDUCTOR DEVICES
    55.
    发明申请
    PACKAGE FOR POWER SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220208745A1

    公开(公告)日：2022-06-30

    申请号：US17219123

    申请日：2021-03-31

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K. Koduri ,  Steven R. Tom ,  Paul Brohlin

    IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/31

    Abstract: In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

    MULTI-LEAD ADAPTER
    56.
    发明申请
    MULTI-LEAD ADAPTER 有权

    公开(公告)号：US20220077030A1

    公开(公告)日：2022-03-10

    申请号：US17528087

    申请日：2021-11-16

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K. Koduri ,  Abram M. Castro

    IPC: H01L23/495 ,  H01L23/50

    Abstract: In some examples, a device comprises an electronic component having multiple electrical connectors, the multiple electrical connectors configured to couple to a printed circuit board (PCB) and having a first footprint. The device also comprises a multi-lead adapter comprising multiple rows of leads arranged in parallel, the leads in the rows configured to couple to the electrical connectors of the electronic component and having a second footprint that has a different size than the first footprint.

    Leadframes in semiconductor devices
    57.
    发明授权
    Leadframes in semiconductor devices 有权

    公开(公告)号：US11152322B2

    公开(公告)日：2021-10-19

    申请号：US16150986

    申请日：2018-10-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sreenivasan K. Koduri

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

    Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

    Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies
    60.
    发明申请
    Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies 审中-公开
    集成电路模块之间磁性无线传输的悬臂引线框支撑结构

    公开(公告)号：US20150325501A1

    公开(公告)日：2015-11-12

    申请号：US14275762

    申请日：2014-05-12

    Applicant: Texas Instruments Incorporated

    Inventor： Benjamin Michael Sutton ,  Sreenivasan K. Koduri ,  Subhashish Mukherjee

    IPC: H01L23/495

    CPC classification number: H01L23/49503 ,  H01L23/4951 ,  H01L23/5227 ,  H01L2224/48247 ,  H01L2924/0002

    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

    Abstract translation: 耦合器件使用引线框提供电隔离，引线框被配置为以共面方式支撑两个集成电路芯片。 每个芯片都包含一个电感耦合线圈。 引线框架包括用于附接接合线以耦合到两个集成电路芯片的一组接合焊盘。 两个分离的芯片连接焊盘支持两个芯片。 每个管芯附接垫被配置成用多个悬臂指状物支撑两个集成电路芯片中的一个。

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