公开(公告)号：US20160111527A1

公开(公告)日：2016-04-21

申请号：US14979594

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Abstract translation: 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。

公开(公告)号：US20150357190A1

公开(公告)日：2015-12-10

申请号：US14312707

申请日：2014-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract translation: 公开了一种具有鳍状结构的半导体器件。 半导体器件包括：衬底; 基板上的鳍状结构; 以及在鳍状结构的顶表面和侧壁的一部分上的外延层，其中外延层和鳍状结构在其间包括锗浓度的线性梯度。

公开(公告)号：US09184292B2

公开(公告)日：2015-11-10

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L21/764 ,  H01L29/165 ,  H01L21/311 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/314 ,  H01L21/318 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。

公开(公告)号：US20150249142A1

公开(公告)日：2015-09-03

申请号：US14698828

申请日：2015-04-28

Applicant: United Microelectronics Corp.

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

IPC: H01L29/66 ,  H01L21/263 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract translation: 一种形成具有金属栅极的半导体结构的方法。 首先，提供半导体衬底。 随后，至少在半导体衬底上形成栅极结构。 之后，形成围绕栅结构的间隔结构。 然后，形成层间电介质。 之后，对层间电介质进行平面化处理。 然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。 暴露于开口的间隔结构的部分被去除以扩大开口。 之后，通过开口完全除去牺牲层。 最后，形成栅极导电层以填充开口。

公开(公告)号：US09076784B2

公开(公告)日：2015-07-07

申请号：US14454727

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09024393B2

公开(公告)日：2015-05-05

申请号：US14140546

申请日：2013-12-26

Applicant: United Microelectronics Corp.

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US08951884B1

公开(公告)日：2015-02-10

申请号：US14079648

申请日：2013-11-14

Applicant: United Microelectronics Corp.

Inventor： Hung-Lin Shih ,  Jei-Ming Chen ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Kuan-Hsien Li

IPC: H01L21/76 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/401

Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

Abstract translation: 一种用于形成FinFET结构的方法包括提供衬底，第一区和限定在衬底上的第二区，分别在第一区和第二区内的衬底上设置第一鳍结构和第二鳍结构。 第一氧化物层覆盖第一鳍结构和第二鳍结构。 接下来，依次在基板和第一氧化物层上完全形成第一保护层和第二保护层，去除第一区域内的第二保护层，然后去除第一区域内的第一保护层。 之后，同时除去覆盖第二区域内的第一鳍结构和第二保护层的第一氧化物层，形成第二氧化物层以覆盖第一鳍结构。

公开(公告)号：US20140361386A1

公开(公告)日：2014-12-11

申请号：US14465579

申请日：2014-08-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。

公开(公告)号：US20140213034A1

公开(公告)日：2014-07-31

申请号：US13752408

申请日：2013-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lung Chang ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Jui-Min Lee ,  Keng-Jen Lin ,  Chin-Fu Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

Abstract translation: 形成隔离结构的方法包括以下步骤。 在基板上形成硬掩模层，并且在基板和硬掩模层中形成沟槽。 形成保护层以覆盖沟槽和硬掩模层。 第一隔离材料被填充到沟槽中。 执行蚀刻工艺以蚀刻第一隔离材料的一部分。

公开(公告)号：US20140106557A1

公开(公告)日：2014-04-17

申请号：US14140546

申请日：2013-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。