公开(公告)号：US20210125921A1

公开(公告)日：2021-04-29

申请号：US17140146

申请日：2021-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Li Wang ,  Kai Cheng

IPC: H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.

公开(公告)号：US10923599B2

公开(公告)日：2021-02-16

申请号：US16408415

申请日：2019-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Li Wang ,  Kai Cheng

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/768 ,  H01L29/78

Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.

公开(公告)号：US10854529B2

公开(公告)日：2020-12-01

申请号：US16170067

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/06 ,  H01L23/367 ,  H01L21/48

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US20200006117A1

公开(公告)日：2020-01-02

申请号：US16561026

申请日：2019-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

公开(公告)号：US20190355812A1

公开(公告)日：2019-11-21

申请号：US16017840

申请日：2018-06-25

Applicant: United Microelectronics Corp.

Inventor： Wen-Shen Li ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Xingxing Chen ,  Chee-Hau Ng

IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/306

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

公开(公告)号：US20190221518A1

公开(公告)日：2019-07-18

申请号：US16122897

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/45 ,  H03F3/16 ,  H01L21/768 ,  H01L21/321 ,  H01L21/84

CPC classification number: H01L23/5283 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/7835 ,  H03F3/16 ,  H03F2200/294

Abstract: A semiconductor device includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

公开(公告)号：US20190214497A1

公开(公告)日：2019-07-11

申请号：US15892373

申请日：2018-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7824 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66681

Abstract: A semiconductor device includes: a first gate structure on a substrate; a first drain region having a first conductive type adjacent to one side of the first gate structure; a source region having the first conductive type adjacent to another side of the first gate structure; and a first body implant region having a second conductive type under part of the first gate structure.

公开(公告)号：US20190214458A1

公开(公告)日：2019-07-11

申请号：US15893715

申请日：2018-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L21/763 ,  H01L21/762 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.

公开(公告)号：US20250072092A1

公开(公告)日：2025-02-27

申请号：US18948563

申请日：2024-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A method of manufacturing a multi-finger transistor structure is provided in the present invention, including forming shallow trench isolations in a substrate to define multiple active areas, forming a gate structure on the substrate, wherein the gate structure includes multiple gate parts and multiple connecting parts, and each gate part traverses over one of the active area, and each connecting part alternatively connect one end and the other end of two adjacent gate parts, so as to form meander gate structure.

公开(公告)号：US12191367B2

公开(公告)日：2025-01-07

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  Jinyu Liao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.