公开(公告)号：JPH0659700A

公开(公告)日：1994-03-04

申请号：JP873092

申请日：1992-01-21

Applicant: YAMAHA CORP

Inventor： USUI AKIRA

IPC: G10L19/00 ,  H03M7/30 ,  G10L9/18

Abstract: PURPOSE:To realize a high compressive factor while keeping the quality of voice in combination with an usual voice coder in a simple structure by decreasing a sampling frequency and correspondingly decreasing an original voice data frequency as well for data compression. CONSTITUTION:A voice data compressor is provided with means 6 to convert voice data into 1/N frequency data in accordance with 1/N frequency pulse signals in a sampling frequency when voice data given by sampling voice signals in a certain sampling frequency is compressed. In this way, the frequency of input data is compressed to 1/N for sampling in an 1/N sampling frequency, and so the spectrum envelope shape of original voice signals is reserved in the all-over compressed form. Consequently, a high frequency area is free from sacrifice which occurs when the sampling frequency is compressed in a simple thinning manner.

公开(公告)号：JPH0612862B2

公开(公告)日：1994-02-16

申请号：JP23106086

申请日：1986-09-29

Applicant: YAMAHA CORP

Inventor： USUI AKIRA

IPC: H03H21/00 ,  G11B20/10 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06

公开(公告)号：JPH0544858B2

公开(公告)日：1993-07-07

申请号：JP20096384

申请日：1984-09-26

Applicant: YAMAHA CORP

Inventor： HAGINO KYOSHI ,  USUI AKIRA

IPC: H04Q9/00 ,  H04L12/28

公开(公告)号：JPH02141116A

公开(公告)日：1990-05-30

申请号：JP29536188

申请日：1988-11-22

Applicant: YAMAHA CORP

Inventor： TORII JUNJI ,  USUI AKIRA ,  TAKEUCHI RENICHI ,  YAMAMURA MASAMITSU ,  YAMAMOTO YUSUKE

IPC: H03H17/00 ,  H03H17/02

Abstract: PURPOSE:To make the title circuit adaptive to various input timing specifications while employing a fixed system clock by detecting an input signal representing a sampling period so as to start the arithmetic processing and stopping the operation when the operation with a specific step number is finished. CONSTITUTION:A BIC bit clock whose period is FB is inputted, a word clock SDSY and 16-bit serial data SDI for L and R channels are inputted to an S/P conversion section 11 for each sampling period FW(=1/fs). Thus, an output word clock WCO having a frequency 8 times the input sampling frequency fs is generated. When the trailing of the output word clock WCO is detected by an arithmetic control section 18, a microprogram is executed to the arithmetic section 12. When the microprogram with a prescribed step number is executed, the arithmetic section 12 is in standby for a period till the trailing of the output word clock WCO is detected next.