公开(公告)号：US20110269288A1

公开(公告)日：2011-11-03

申请号：US13182285

申请日：2011-07-13

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成CoSi 2的方法，形成场效应晶体管的方法以及形成导电触点的方法。 在一个实施方案中，形成CoSi 2的方法包括在含硅衬底上形成包含MSix的基本非晶层，其中“M”至少包括除钴以外的一些金属。 包含钴的层沉积在基本上无定形的含MSix的层上。 将衬底退火有效地将含钴层的钴扩散通过基本上无定形的含MSix层并与含硅衬底的硅结合，以在基本上无定形的含MSix层下形成CoSi 2。 考虑了其他方面和实现。

公开(公告)号：US20110095357A1

公开(公告)日：2011-04-28

申请号：US12986487

申请日：2011-01-07

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L29/792 ,  H01L21/3205

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

公开(公告)号：US07923322B2

公开(公告)日：2011-04-12

申请号：US11234328

申请日：2005-09-23

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC: H01L21/8242

CPC classification number: H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.

Abstract translation: 形成电容器的方法包括在衬底上形成第一电容器电极。 在第一电容器电极上形成基本上结晶的电容器电介质层。 具有基本上结晶的电容器电介质层的衬底设置在化学气相沉积反应器内。 这种衬底具有暴露的基本无定形的材料。 包含硅的气态前体在有效基本上选择性地在基本上结晶的电容器电介质层上沉积多晶硅相对于暴露的基本无定形材料的条件下被馈送到化学气相沉积反应器，并且多晶硅形成第二电容器电极。

公开(公告)号：US07510966B2

公开(公告)日：2009-03-31

申请号：US11074106

申请日：2005-03-07

Applicant: Qi Pan ,  Jiutao Li ,  Yongjun Jeff Hu ,  Allen McTeer

Inventor： Qi Pan ,  Jiutao Li ,  Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L21/4763

CPC classification number: H01L21/76838 ,  H01L21/28061 ,  H01L21/28518 ,  H01L21/2855 ,  H01L23/485 ,  H01L27/10891 ,  H01L29/4933 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括导电线，形成导电线的方法，以及在多晶硅晶体管栅极线上制造钛硅化物时还原钛硅化物聚集的方法。 在一个实施方案中，形成导电线的方法包括在衬底上提供含硅层。 在含硅层之上形成导电层。 在该导电层上形成一个含有MSixNy的层，其中“x”为0至3.0，“y”为0.5至10，“M”为Ta，Hf，Mo和W中的至少一种。 在包括MSixNy的层上形成包含MSI的层，其中“z”为1至3.0。 在包含MSiz的层上形成含TiSia层，其中“a”为1至3.0。 将包含硅的层，导电层，含MSixNy的层，包含MSiz的层和含TiSia的层图案化成包括导电线的堆叠。 考虑了其他方面和实现。

公开(公告)号：US06951786B2

公开(公告)日：2005-10-04

申请号：US09951324

申请日：2001-09-12

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L21/285 ,  H01L21/8238

CPC classification number: H01L21/28518

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate. The substrate is annealed under conditions effective to diffuse at least some of at least one of the refractory metal and the silicon through the buffering layer to form a silicide of the refractory metal, with the buffering layer during the annealing reducing silicon consumption from the region over that which would otherwise occur under the same annealing conditions were the buffering layer not present. The invention also encompasses a method of forming a stack of refractory metal nitride over refractory metal silicide over silicon includes providing a silicon comprising substrate.

Abstract translation: 本发明包括在包含硅的衬底上形成硅化物互连的方法。 在一个实施方案中，在包含硅的衬底的需要硅化物互连的区域上形成包括金属和非金属杂质的第一层。 包含第二层的元素金属形成在第一层上。 将衬底退火以在至少第二层的元素金属和衬底区域的硅之间引起反应，以形成第二层的元素金属的硅化物。 在另一个考虑的方面中，在包含硅的衬底上形成硅化物互连的方法包括提供缓冲层以在包含难熔金属的层和衬底的含硅区域之间的硅扩散。 衬底在有效地通过缓冲层扩散难熔金属和硅中的至少一种的至少一些的条件下进行退火，以形成难熔金属的硅化物，退火期间的缓冲层减少了来自该区域的硅消耗 否则在相同退火条件下发生的缓冲层不存在。 本发明还包括在硅之上的难熔金属硅化物上形成难熔金属氮化物堆叠的方法，包括提供含硅的衬底。

公开(公告)号：US06933580B2

公开(公告)日：2005-08-23

申请号：US10614538

申请日：2003-07-03

Applicant: Gary Chen ,  Li Li ,  Yongjun Jeff Hu

Inventor： Gary Chen ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32134

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract translation: 金属氮化物和金属氮氧化合物通常在金属硅化物上形成。 这些挤压可能导致短路并降低加工产量。 本发明公开了一种选择性地去除这种挤出物的方法。 在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。 在另一个实施方案中，湿蚀刻包括调节蚀刻的pH以选择性地相对于字线中的其它物质去除某些挤出物的碱。 因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

公开(公告)号：US06734089B1

公开(公告)日：2004-05-11

申请号：US10345542

申请日：2003-01-16

Applicant: Yongjun Jeff Hu ,  Satish Bedge ,  Kevin Torek

Inventor： Yongjun Jeff Hu ,  Satish Bedge ,  Kevin Torek

IPC: H01L213205

CPC classification number: H01L27/10891 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L27/11

Abstract: Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the process flow to remove or weaken certain layers formed in the wordlines. For instance, an SiNx layer and a crystallized W2N layer may form during the fabrication of the wordline. While the layers may provide certain advantages at certain points in the fabrication process, they may be undesirable at subsequent points. One or more anneal processes may be implemented at various points in the processing to eliminate the crystallized W2N layer and weaken the SiNx layer.

Abstract translation: 制造半导体器件的制造技术。 更具体地，提供了用于在存储器件中制造字线的技术。 可以将比热处理添加到工艺流程中以去除或削弱在字线中形成的某些层。 例如，在制作字线期间可能形成SiNx层和结晶化的W2N层。 虽然这些层可以在制造过程的某些点提供某些优点，但是它们在随后的点处可能是不期望的。 可以在处理的各个点处实施一个或多个退火工艺，以消除结晶的W2N层并削弱SiNx层。

公开(公告)号：US06693354B2

公开(公告)日：2004-02-17

申请号：US10234577

申请日：2002-08-30

Applicant: Gary Chen ,  Li Li ,  Yongjun Jeff Hu

Inventor： Gary Chen ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L2945

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32134

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract translation: 金属氮化物和金属氮氧化合物通常在金属硅化物上形成。 这些挤压可能导致短路并降低加工产量。 本发明公开了一种选择性地去除这种挤出物的方法。 在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。 在另一个实施方案中，湿蚀刻包括调节蚀刻的pH以选择性地相对于字线中的其它物质去除某些挤出物的碱。 因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

公开(公告)号：US06559053B1

公开(公告)日：2003-05-06

申请号：US09631329

申请日：2000-08-03

Applicant: Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz. The device structure may be subjected to a rapid thermal process in a nitrogen containing atmosphere or, alternatively, an atmosphere devoid of nitrogen.

Abstract translation: 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 通常，钝化层包括SixOyNz。 装置结构可以在含氮气氛中进行快速热处理，或者在没有氮的气氛中进行快速热处理。

公开(公告)号：US06541390B2

公开(公告)日：2003-04-01

申请号：US09997917

申请日：2001-11-30

Applicant: Whonchee Lee ,  Yongjun Jeff Hu

Inventor： Whonchee Lee ,  Yongjun Jeff Hu

IPC: H01L21302

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide. An etching composition including a mineral acid and a peroxide, preferably, HCl and hydrogen peroxide, is also described. The etching methods and compositions may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.

Abstract translation: 用于集成电路制造的蚀刻方法包括在衬底组件上提供金属氮化物层，在金属氮化物层的第一部分上提供钴硅化物的区域，以及在金属氮化物层的第二部分上提供钴区域。 用至少一种包含无机酸和过氧化物的溶液除去钴的区域和金属氮化物层的第二部分。 无机酸可以选自HCl，H 2 SO 4，H 3 PO 4，HNO 3和稀释的HF，优选无机酸是HCl），过氧化物可以是过氧化氢。 此外，去除钴的区域和金属氮化物层的第二部分可以包括一步法或两步法。 在一步法中，用包含无机酸和过氧化物的单一溶液除去钴的区域和金属氮化物层的第二部分。 在两步法中，用含有无机酸和过氧化物的第一溶液除去钴的区域，并用含有过氧化物的第二溶液除去金属氮化物层的第二部分。 还描述了包含无机酸和过氧化物，优选HCl和过氧化氢的蚀刻组合物。 蚀刻方法和组合物可以用于形成诸如字线，栅电极，局部互连等的结构。