公开(公告)号：US11822934B2

公开(公告)日：2023-11-21

申请号：US17341054

申请日：2021-06-07

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Roberto Colombo ,  Om Ranjan

IPC: G06F11/10 ,  G06F9/445 ,  G06F13/36 ,  H04L9/06 ,  H04L9/32

CPC classification number: G06F9/44505 ,  G06F11/1004 ,  G06F13/36 ,  H04L9/0643 ,  H04L9/3247

Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.

公开(公告)号：US11764807B2

公开(公告)日：2023-09-19

申请号：US17858782

申请日：2022-07-06

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Roberto Colombo

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/611

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.

公开(公告)号：US20230267087A1

公开(公告)日：2023-08-24

申请号：US18309103

申请日：2023-04-28

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  G06F9/54

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F11/0772 ,  G06F11/0739 ,  H04L12/403 ,  G06F11/0757 ,  G05B19/042 ,  G06F9/542 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US11695589B2

公开(公告)日：2023-07-04

申请号：US17539936

申请日：2021-12-01

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Rolf Nandlinger

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US20230133385A1

公开(公告)日：2023-05-04

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F11/36

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

公开(公告)号：US11520721B2

公开(公告)日：2022-12-06

申请号：US16933752

申请日：2020-07-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/00 ,  G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US20220334865A1

公开(公告)日：2022-10-20

申请号：US17657856

申请日：2022-04-04

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F9/455 ,  G06F11/07

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

公开(公告)号：US20220318173A1

公开(公告)日：2022-10-06

申请号：US17806587

申请日：2022-06-13

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20220191059A1

公开(公告)日：2022-06-16

申请号：US17539936

申请日：2021-12-01

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred RENNIG ,  Rolf NANDLINGER

IPC: H04L12/40 ,  G06F13/42 ,  G06F13/40

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US11321492B2

公开(公告)日：2022-05-03

申请号：US17107183

申请日：2020-11-30

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio ,  Lorenzo Re Fiorentin

IPC: G06F9/448 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F21/71 ,  G06F21/60 ,  H04L9/06 ,  G06F11/07 ,  G06F21/57 ,  G06F21/72 ,  G06F21/77 ,  H03K19/17728

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.