Abstract:
An electrophoretic display device comprises a plurality of pixels, each pixel has a cell area containing a plurality of charged pigment particles (43) dispersed between two opposite electrodes (411, 421), and a semiconducting passivation layer (45) is provided on one or both of the two opposite electrodes (411, 421). The semiconducting passivation layer can be made of MOx/y, MSx/y, or MNx/y where M is a metal or semiconductor such as Al, Sn, Zn, Si, Ge, Ni, Ti, or Cd; x is a positive integer; and y is independently a non-zero positive integer. The semiconducting passivation layer may have a doped Si, ZnOx/y, ZnSx/y, CdSx/y and TiOx/y or a III-V type semiconducting material. The semiconducting passivation layer can be doped with a dopant which can be an n-type donor or a p-type acceptor, the n-type donor is N, P, As or F; and the p-type acceptor is B, Al, Ga, In, Be, Mg or Ca.
Abstract:
A first film (8) is formed between a substrate (1) constituting an optical waveguide device (10) and a signal electrode (3) and ground electrodes (5), (6). A second film (9) is formed between the substrate (1) and a signal electrode (4) and ground electrodes (6), (7). The substrate (1), an optical waveguide (2), the signal electrode (3), the ground electrodes (5), (6) and the first film (8) constitute an optical phase modulator (10A). The substrate (1), the optical waveguide (2), the signal electrode (4), the ground electrodes (6), (7) and the second film (9) constitute an optical intensity modulator (10B). The optical waveguide element (10) is constituted by integrating the optical phase modulator(10A) and the optical intensity modulator (10B).
Abstract:
An array substrate for an LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to prevent breaking of a data line using first and second topology difference buffering units, thereby lowering an error rate of an LC panel. A gate line(202) and a data line(220) are crossed on a substrate to define a pixel area. A switching device is configured at an intersection between the gate line and the data line. A pixel electrode(226) is configured in the pixel area. First and second topology difference buffering units(206,208) are configured in both sides of the gate line at a position crossing with the data line, and buffer a topology difference by the side of the gate line.
Abstract:
TFT(43)를 절연 기판(42)상에 형성하고 이 TFT(43)를 피복하기 위하여 층간 절연막인 감광성 수지(44) 막을 형성한다. 산재된 원형 차광부가 제공된 제1 포토마스크 및 제2 포토마스크를 이용하여 2회 노출을 실시하여 감광성 수지(44) 및 TFT(43) 이외의 영역에 있는 매끄러운 오목부 및 볼록부에 접촉공(66)을 형성한다. 또한 감광성 수지(44)상에 MoN 막(45) 및 반사 전극(46)을 연속해서 적층한다. MoN 막(45)중의 N 2 함량을 총 5원자% 내지 30 원자%로 만들어서 MoN 막(45)이 감광성 수지(44)에 대하여 강한 접착력을 수득할 수 있고 에칭 속도 감소를 방지할 수 있다.
Abstract:
PURPOSE: A wiring board is provided to improve an adhesion property with an insulating film in a metal film formed on the insulating film. CONSTITUTION: A TFT(43) is formed on the insulating substrate(42), and a film of the photosensitive resin(44) which covers a TFT is formed. Two times of exposure are performed by the first and second photomasks in which circular light shielding parts waste distributed, a contact hole(66) is formed in the photosensitive resin(44), and a smooth ruggedness is formed in the area other than the TFT(43). Furthermore, a MoN film(45) and a reflector electrode(46) are sequentially laminated on the photosensitive resin(44). In this case, a high adhesion strength of the MoN layer(45) to the photosensitive resin can be obtained by setting the N2 content in the MoN film(45) from 5 atomic % to 30 atomic %, and the degradation of the etching rate can be suppressed.
Abstract in simplified Chinese:一种液晶显示设备之数组基板,包含有:位于基板上的闸极线和数据线,闸极线与数据线交叉以定义像素区域;位于闸极线与数据线之间的绝缘层;与闸极线与数据线之交叉处相邻的开关组件;连接开关组件的像素电极,像素电极位于像素区域内;以及第一缓冲图案,其位于其中一条闸极线或数据线之第一侧且与之位于同一层,并与另一条闸极线或数据线重叠。
Abstract:
The present application discloses a mother substrate comprising a first region comprising a plurality of display substrate units; and a second region; the first region comprises a buffer layer on and in contact with a base substrate, the second region comprises a mat layer on and in contact with the base substrate for reducing segment difference between the first region and the second region.