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    General purpose, programmable media processor
    66.
    发明公开
    General purpose, programmable media processor 失效
    程序员Allzweckmedienprozessor zurAusführungvon Gruppengleitkommabefehlen

    公开(公告)号：EP1876524A2

    公开(公告)日：2008-01-09

    申请号：EP07111351.8

    申请日：1996-08-16

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

    IPC: G06F9/30 ,  G06F15/76

    CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

    Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

    Abstract translation: 一种用于处理和发送媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包括执行单元（100），其通过媒体数据流保持基本上峰值数据。 执行单元（100）包括动态分离多精度运算单元（102），可编程开关（104）和可编程扩展数学元件（106）。 高带宽外部接口（124）以基本上峰值的速率将媒体数据流提供给通用寄存器文件（110）和执行单元。 提供存储器管理单元，以及指令和数据高速缓冲存储器/缓冲器（118,120）。 通用的可编程媒体处理器（12）被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。

    SYSTEM AND METHOD TO IMPLEMENT A CROSS-BAR SWITCH OF A BROADBAND PROCESSOR
    67.
    发明公开
    SYSTEM AND METHOD TO IMPLEMENT A CROSS-BAR SWITCH OF A BROADBAND PROCESSOR 审中-公开
    系统和方法是实现宽带处理器的CROSS-BASS AGE

    公开(公告)号：EP1236090A1

    公开(公告)日：2002-09-04

    申请号：EP00910150.2

    申请日：2000-02-11

    Applicant: Microunity Systems Engineering, Inc.

    Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

    IPC: G06F9/30

    CPC classification number: G06F7/76 ,  G06F9/30018

    Abstract: The present invention provides a cross-bar circuit (100) that implements a switch (115) of a broadband processor. The cross-bar circuit (100) includes: a switch circuit (115) which includes 2m.2n:1 multiplexor circuits (202-204) where each of the 2n:1 multiplexor circuits (202-204) has a unique n-bit index input, one disable input, and a 2n-bit wide source input receives an n-bit index at the n-bit index input, a disable bit at the disable input, and the 2n-bit input source word at the 2n-bit wide source input, and decodes the n-bit index either to select and output as an output destination bit one bit from the 2n-bit input source word if the disable bit has a logic low value; a cache memory (110) that has 2m cache datapath inputs; and 2m cache index input; and a control circuit (105) that has a plurality of control inputs receives the partially decoded instruction information on the plurality of control inputs, provides a second set of the n-bit indexes for the switch circuit (115), and provides the disable bits for the switch circuit (115) where the control circuit (105) is logically coupled to the switch circuit (115) and to the cache memory (110).

    A VERTEX BASED GEOMETRY ENGINE SYSTEM FOR USE IN INTEGRATED CIRCUIT DESIGN
    68.
    发明公开
    A VERTEX BASED GEOMETRY ENGINE SYSTEM FOR USE IN INTEGRATED CIRCUIT DESIGN 失效
    顶点几何基于机器系统所使用的集成电路模型

    公开(公告)号：EP0979448A1

    公开(公告)日：2000-02-16

    申请号：EP97935017.0

    申请日：1997-07-21

    Applicant: Microunity Systems Engineering, Inc.

    Inventor： LAIDIG, Thomas, L.

    IPC: G06F9/00 ,  G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.

    BiCMOS LOGIC CIRCUIT
    69.
    发明公开
    BiCMOS LOGIC CIRCUIT 失效
    BiCMOS逻辑电路。

    公开(公告)号：EP0628226A1

    公开(公告)日：1994-12-14

    申请号：EP93907156.0

    申请日：1993-02-23

    Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

    Inventor： ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

    IPC: H03K19 ,  H03K17

    CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

    Abstract: Circuit logique BICMOS amélioré (70) utilisant une paire de transistors bipolaires (21, 22) à couplage par émetteurs pour comparer de manière différentielle un signal d'entrée (Vin) et un niveau de référence logique (VBIAS). Chaque transistor bipolaire est chargé de manière résistive par un réseau de transistors (26, 27) à semiconducteur à grille isolée par oxyde métallique à canal P (PMOS) couplés en parallèle. La grille d'au moins une des combinaisons parallèles de transistors est couplée à un signal de commande (VREF2) fournissant une résistance de charge variable. De préférence, le signal de commande est fourni par un réseau de retour (52, 53) servant à maintenir à une valeur constante l'excursion de tension constante dans le réseau, malgré les variations de température.

    BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS
    70.
    发明公开
    BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS 失效
    具有改进的STROMVERSTÄRKUNGS-和突破性的功能BOPOLARTRANSISTOR。

    公开(公告)号：EP0609351A1

    公开(公告)日：1994-08-10

    申请号：EP92922539.0

    申请日：1992-10-19

    Applicant: MicroUnity Systems Engineering, Inc.

    Inventor： MATTHEWS, James, A.

    IPC: H01L29 ,  H01L21

    CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

    Abstract: Transistor bipolaire possédant un émetteur (25), une base (31) et un collecteur (30). Il comprend une zone de base intrinsèque (33) à zones latérales étroites (p-) et à zone centrale plus large (37). Les zones latérales sont contiguës à la zone dopée (31), et la zone centrale (37) se trouve sous l'émetteur (25). Le profil de dopage latéral de la base est tel que les concentrations de dopage dans la zone dopée (31) et la zone centrale (37) sont relativement élevées par rapport à celles dans les zones latérales étroites (p-) de la base intrinsèque (33). L'association des zones latérales étroites (p-) au profil de dopage latéral de la base limite l'étendue de la zone de déplétion à l'intérieur de la base, ce qui assure une réduction de la tension de claquage du transistor sans entraîner une perte du gain en courant.

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