公开(公告)号：WO1993014445A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000456

申请日：1993-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

IPC: G03F09/00

CPC classification number: G03F1/36 ,  G03F7/70433 ,  G03F7/70441

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

公开(公告)号：WO1993020482A1

公开(公告)日：1993-10-14

申请号：PCT/US1993003126

申请日：1993-03-29

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, Jang, Fung ,  MATTHEWS, James, A.

IPC: G03F07/20

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A method of printing a sub-resolution device feature (16) having first and second edges spaced in close proximity to one another on a semiconductor substrate (20) includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment (11) which corresponds to the first edge. The first mask image segment is then exposed with radiation (10) using an imaging tool (12) to produce a first pattern edge gradient (14). The first pattern edge gradient defines the first edge of the feature in the material. A second mask image segment (13) is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation (10) to produce a second pattern edge gradient (17) which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.

Abstract translation: 印刷具有在半导体衬底（20）上彼此靠近彼此间隔开的第一和第二边缘的子分辨率器件特征（16）的方法包括以下步骤：首先在衬底上沉积辐射敏感材料，然后提供 第一掩模图像段（11），其对应于第一边缘。 然后使用成像工具（12）用辐射（10）将第一掩模图像段曝光以产生第一图案边缘梯度（14）。 第一个图案边缘渐变定义材料中特征的第一个边缘。 然后对应于第二特征边缘提供第二掩模图像段（13）。 该第二掩模图像段暴露于辐射（10）以产生限定特征的第二边缘的第二图案边缘梯度（17）。 一旦辐射敏感材料已经开发出来，二维特征就在基片上再现。

公开(公告)号：WO1993008599A1

公开(公告)日：1993-04-29

申请号：PCT/US1992008905

申请日：1992-10-19

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L23/00

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

Abstract: A bipolar transistor having an emitter (25), a base (31), and a collector (30) includes an intrinsic base (33) region having narrow side areas (p-) and a wider central area (37). The side areas are located adjacent to the extrinsic base region (31), while the central area (37) is disposed underneath the emitter (25). The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region (31) and the central area (37) are relatively high compared to the doping concentration of the narrow side areas (p-) of the intrinsic base (33). The combination of the narrow side areas (p-) and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract translation: 具有发射极（25），基极（31）和集电极（30）的双极晶体管包括具有窄侧面积（p-）和较宽中心区域（37）的本征基极（33）区域。 侧面区域邻近外部基极区域（31）定位，而中心区域（37）设置在发射器（25）的下方。 定制基底的横向掺杂分布，使得非本征区域（31）和中心区域（37）中的掺杂浓度相对于本征基底的窄边区域（p-）的掺杂浓度相对较高 33）。 窄边区域（p-）和横向基极掺杂曲线的组合限制了基极内的耗尽区域，从而降低晶体管的穿通电压而不损失β。

公开(公告)号：WO1993017498A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001894

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

IPC: H03K17/16

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.

Abstract translation: 改进的BiCMOS逻辑电路（70）利用发射极耦合的双极晶体管（21,22）来差分地比较输入信号（Vin）与逻辑参考电平（VBIAS）。 每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管（26,27）的网络进行电阻负载。 晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号（VREF2）的栅极。 控制信号优选地由反馈网络（52,53）提供，反馈网络（52,53）通过温度在网络上保持恒定的电压摆幅。

公开(公告)号：WO1992017745A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002622

申请日：1992-03-31

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: F28F07/02

CPC classification number: F28F3/12 ,  F28D2021/0029 ,  F28F2260/02 ,  H01L23/473 ,  H01L2924/0002 ,  Y10T29/49366 ,  Y10T29/49368 ,  H01L2924/00

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates (10), laminated together to form a block (18). Each plate has a pair of holes (14, 15) cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

公开(公告)号：WO1991011019A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000211

申请日：1991-01-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L21/225

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136 ,  H01L2924/00

Abstract: A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing the interconnection of the MOS and NPN transistors.

公开(公告)号：WO1993017461A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001203

申请日：1993-02-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0826 ,  Y10S257/927

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region (11) formed above a more heavily-doped n+ layer (12). Directly above the collector is a p-type base which has an extrinsic region (17) disposed laterally about an intrinsic region (18). An n+ emitter (20) is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region (15) disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract translation: 显示抑制Kirk效应的双极结型晶体管（BJT）包括形成在更重掺杂的n +层（12）上方的轻掺杂的n型集电极区域（11）。 集电极的正上方是p型基体，其具有围绕本征区域横向设置的非本征区域（17）。 n +发射极（20）位于本征基极区的正上方。 BJT还包括直接位于本征基极区下方的局部n +区（15），这显着增加了晶体管的电流处理能力。

公开(公告)号：WO1992020160A1

公开(公告)日：1992-11-12

申请号：PCT/US1992003512

申请日：1992-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A. ,  ROSSEEL, Geert

IPC: H03K17/16

CPC classification number: H03K19/09448

Abstract: A BiCMOS logic circuit (20) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (VIN) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a p-channel metal-oxide-semiconductor (PMOS) transistor (26, 27). An emitter follower (33 or 34), having its base coupled to the collector of one of the bipolar transistors and its collector connected to the first power supply potential (GND), provides the output signal. NMOS transistors (24, 36, 37) are used as current sources for biasing the emitter-coupled pair and the emitter follower. A circuit means provides a feedback signal coupled to the gates of the PMOS transistors for dynamically controlling the load resistance presented to said emitter coupled pair.

公开(公告)号：WO1991020084A1

公开(公告)日：1991-12-26

申请号：PCT/US1991004085

申请日：1991-06-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: G11C13/06

CPC classification number: G11C11/18 ,  G02F1/09 ,  G02F1/19 ,  G11C7/005 ,  G11C13/04

Abstract: An optical modulator utilizing a magnetic semiconductor device, whose operation is based on the Hall effect, includes a magnetic material (33) formed on a semiconductor substrate (27). When an incoming beam of light (105) having a dominant polarization direction is directed onto the magnetic material (33) it becomes modulated. The result is an outgoing beam of light (106) which has a rotated plane of polarization when compared to the dominant polarization direction. The direction of the rotated plane of polarization is indicative of the information stored in the magnetic material (33). The modulator of the present invention further includes a means for writing the information to the magnetic material and a semiconductor sensor means (35) for electrically verifying the contents of the magnetic material (33).

公开(公告)号：WO1991011006A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000331

申请日：1991-01-16

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: G11C11/18

CPC classification number: G11C11/18

Abstract: A non-volatile, static magnetic memory device (10), whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch (33) which stores data in the form of a magnetic field, a semiconductor Hall bar (14, 15, and 17) and a pair of integrally-formed bipolar transistors (28 and 29) used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases (18 and 19) of the bipolar transistors (28 and 29) are ohmically coupled to the Hall bar to sense the Hall voltage, the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.