公开(公告)号：US20040174742A1

公开(公告)日：2004-09-09

申请号：US10796995

申请日：2004-03-11

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Motoki Kanamori ,  Takayuki Tamura ,  Kenji Kozakai ,  Atsushi Shikata ,  Shinsuke Asari

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C2207/229

Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.

公开(公告)号：US20040145955A1

公开(公告)日：2004-07-29

申请号：US10757441

申请日：2004-01-15

Applicant: Renesas Technology Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

IPC: G11C029/00

CPC classification number: G11C5/14 ,  G11C5/147

Abstract: A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

公开(公告)号：US20040142512A1

公开(公告)日：2004-07-22

申请号：US10754545

申请日：2004-01-12

Applicant: Renesas Technology Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Shinji Tojo ,  Shinya Kanamitsu ,  Seiichi Ichihara

IPC: B23K031/02 ,  H01L021/44

CPC classification number: H01L24/81 ,  G02F1/13452 ,  H01L21/563 ,  H01L21/67138 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/50 ,  H01L24/86 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract translation: 将半导体芯片上的凸极电极和薄膜基板上的引线以高精度连接在一起。 考虑在半导体芯片上的突出电极和薄膜基板上的内部引线相互连接时发生的引线间距的变化，并且预先对内部引线的间距进行校正。 同样地，考虑到将液晶基板上的电极和薄膜基板上的外部引线彼此连接时发生的引线间距的变化，并且预先对外部引线的间距进行校正。

公开(公告)号：US20040124506A1

公开(公告)日：2004-07-01

申请号：US10729950

申请日：2003-12-09

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Renesas Eastern Japan Semiconductor, Inc.

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Hiroyuki Takeno ,  Hiroshi Shimoji ,  Fumio Murakami ,  Keiko Kurakawa

IPC: H01L023/495

CPC classification number: H01L24/97 ,  H01L21/565 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract translation: 旨在提高QFN（四方扁平无铅封装）的生产成本，达到多引脚结构。 在通过模塑形成用于密封半导体芯片的树脂密封构件之后，树脂密封构件的周边部分和引线框架都沿着位于树脂密封构件的内侧（树脂密封构件的中心侧）上的切割线切割 沿着树脂密封构件的外缘延伸的线（成型线），从而覆盖暴露于树脂密封构件的侧面（切割面）的各个引线的整个表面（上下表面和两个侧面） 树脂，从而防止在引线的切割面上发生金属毛刺。

公开(公告)号：US20040107307A1

公开(公告)日：2004-06-03

申请号：US10615923

申请日：2003-07-10

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Masami Hasegawa ,  Yoichi Satoh ,  Yuuji Yanagisawa ,  Yoshio Iioka ,  Yoshimi Kitagawa ,  Makio Uchida

IPC: G06F012/00

CPC classification number: G11C7/1075 ,  G06F13/1689 ,  Y02D10/14

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

Abstract translation: 多端口存储器具有电连接到RAM的访问端口的多个RAM和端口扩展单元。 端口扩展单元包括：输入电路，其允许用于每个存储周期并行地激活RAM的访问控制信息，以通过多个存储周期共同输入;定时发生器，其产生能够串行地规定每个存储周期的内部时钟信号 时钟信号（ck）的一个周期的逻辑电路，以及逻辑电路，其能够在与内部时钟信号同步的每个串行存储器循环中以部分顺序地将输入到输入电路的访问控制信息并行地分配给多个RAM。 端口扩展单元允许访问具有多个RAM的访问端口作为单个多端口存储器。

公开(公告)号：US20030235058A1

公开(公告)日：2003-12-25

申请号：US10452045

申请日：2003-06-03

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiroshi Toyoshima ,  Masahiko Nishiyama

IPC: H02M007/00

CPC classification number: G05F1/56

Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin. And, since the phase compensating resistor can take a considerably high resistance, the same characteristic can be achieved with a low capacitance of the phase compensating capacitor; thereby, the phase compensation becomes possible with a resistor and a capacitor having a smaller size than the pole/zero compensation with the internal supply voltage.

Abstract translation: 本发明旨在提供一种容易实现足够的相位裕度的技术。 电路包括在差分放大器的第二输入端子与低电源电压之间形成有相位补偿电阻器和相位补偿电容器的电源电路。 因此，总增益中的第一极点频率由偏移到较低频率的极点/零点补偿的波德图中的分压电阻级中的第一极点频率决定。 此外，零点消除差分放大器级中的第一极点频率，这降低了相位延迟以确保相位裕度。 并且，由于相位补偿电阻器可以具有相当高的电阻，所以可以通过相位补偿电容器的低电容实现相同的特性; 由此，电阻和电容器的尺寸比内部电源电压的极/零补偿小的相位补偿成为可能。

公开(公告)号：US20030228720A1

公开(公告)日：2003-12-11

申请号：US10446787

申请日：2003-05-29

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Fujio Ito ,  Hiromichi Suzuki

IPC: H01L021/44 ,  H01L021/48

CPC classification number: H01L23/49551 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprising a semiconductor chip with plural electrodes arranged on a main surface thereof, plural leads electrically connected respectively to the plural electrodes on the semiconductor chip, and a resin sealing body which seals the semiconductor chip and the plural leads, wherein the plural leads include first leads and second leads adjacent to the first leads, the first leads having first external connections exposed from a mounting surface of the resin sealing body and positioned near a side face of the resin sealing body, the second leads having second external connections exposed from the mounting surface of the resin sealing body and positioned closer to the semiconductor chip with respect to the first external connections. The first and second leads are fixed to the semiconductor chip. The semiconductor device is suitable for a multi-pin structure and the manufacturing yield thereof is improved.

Abstract translation: 一种半导体器件，包括在其主表面上布置有多个电极的半导体芯片，分别与半导体芯片上的多个电极电连接的多个引线以及密封半导体芯片和多个引线的树脂密封体，其中多个引线 包括与第一引线相邻的第一引线和第二引线，第一引线具有从树脂密封体的安装表面露出并位于树脂密封体的侧面附近的第一外部连接，第二引线具有暴露于第二引线 树脂密封体的安装表面并且相对于第一外部连接更靠近半导体芯片定位。 第一和第二引线固定在半导体芯片上。 半导体器件适用于多引脚结构，并且其制造成品率得到改善。

公开(公告)号：US20030227707A1

公开(公告)日：2003-12-11

申请号：US10448179

申请日：2003-05-30

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yasuhiko Kokami ,  Minoru Kurosawa

IPC: G11B021/02 ,  G11B005/596

CPC classification number: G11B5/54 ,  G11B21/12 ,  G11B21/22

Abstract: In a magnetic disk memory device, the shifting speed of the magnetic head in time of power supply interruption is detected, and a voice coil motor is controlled in accordance with the detected shifting speed to enable the head to be shunted safely and promptly. In a magnetic disk memory device having a spindle motor for revolving a magnetic disk, a magnetic head for reading information from the magnetic disk, a voice coil motor for shifting this magnetic head, and a voice coil motor drive circuit for controlling the drive current of the voice coil motor, the shifting speed of the head in time of power supply interruption is detected on the basis of the back electromotive force generating on the coil of the voice coil motor in time of power supply interruption, there are further provided a retract control circuit for generating a current command value for the voice coil motor drive circuit on the basis of the result of detection and a booster circuit for boosting a voltage resulting from the rectification of the back electromotive force generating in the coil of the spindle motor, wherein the voice coil motor drive circuit and the retract control circuit are operated with the voltage boosted by the booster circuit in time of power supply interruption to control the current to be made to flow to the coil of the voice coil motor and thereby to shunt the magnetic head.

Abstract translation: 在磁盘存储装置中，检测到电源中断时磁头的移动速度，并且根据检测到的移位速度来控制音圈电动机，使头能够安全，及时地分流。 在具有用于旋转磁盘的主轴电动机的磁盘存储装置中，用于从磁盘读取信息的磁头，用于移动该磁头的音圈电动机和用于控制磁头的驱动电流的音圈电动机驱动电路 基于在电源中断时在音圈电动机的线圈上产生的反电动势来检测电源中断时的磁头的移动速度，进一步提供音圈电动机， 基于检测结果产生音圈电动机驱动电路的电流指令值的电路，以及用于升高由主轴电动机的线圈产生的反电动势的整流产生的电压的升压电路，其中， 音圈电机驱动电路和退绕控制电路在电源供电时由升压电路提升的电压进行工作 以控制流向音圈马达的线圈的电流，从而分流磁头。

公开(公告)号：US20030227304A1

公开(公告)日：2003-12-11

申请号：US10443035

申请日：2003-05-22

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Kayoko Saito ,  Mitsugu Kusunoki ,  Hiroyasu Ishizuka ,  Shinichiro Masuda

IPC: H03B001/00 ,  H03K003/00

CPC classification number: H03K5/08 ,  G11C5/14 ,  G11C11/417 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H03K19/00315

Abstract: A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

Abstract translation: 在高电位侧电源和低电位侧电源之间设置有分别垂直于其上堆叠的第一钳位电路和第二钳位电路，用于夹紧不期望的电平电压，并且在第一钳位电路和第二钳位 电路与内部电路的电源耦合。 由于最初设置在内部电路中的电容器与第一钳位电路并联地分配，所以由于电容器的存在而导致的阻抗减小，并且由于芯片中的过电流流动导致的电位差减小。 因此，由于过电流流入芯片的电位差可能降低，并且通过允许更高的过电流可以提高静电绝缘强度。 因此，钳位电路以两级堆叠的阻抗。

公开(公告)号：US20030207214A1

公开(公告)日：2003-11-06

申请号：US10424854

申请日：2003-04-29

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Takuya Futase ,  Tomonori Saeki ,  Mieko Kashi

IPC: G03F007/20 ,  H01L021/66 ,  G01R031/26 ,  H01L021/311 ,  H01L021/31 ,  H01L021/469 ,  H01L021/20 ,  G03F007/40 ,  G03F007/16

CPC classification number: C23F1/30 ,  H01L21/32134 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  Y10S134/902

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract translation: 为了防止在半导体批量生产工艺中由过渡金属制成的晶片的污染，本发明的半导体集成电路器件的批量生产方法包括以下步骤：在通过晶片工艺的各个晶片上沉积Ru膜， 通过含有正周期酸和硝酸的水溶液从沉积有Ru膜的单个晶片的器件侧和背面的外边缘部分去除Ru膜，并对其进行处理 所述Ru膜已被去除，涉及光刻步骤，与属于下层步骤的多个晶片（初始元素形成步骤和形成前的布线步骤）具有通用关系的检查步骤或热处理步骤 的栅极绝缘膜）。