公开(公告)号：JP2007208242A

公开(公告)日：2007-08-16

申请号：JP2006347122

申请日：2006-12-25

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： VELOSO ANABELA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/4975 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/66507 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To provide a method of controlling the height of a gate electrode in a silicidation process. SOLUTION: The method of controlling the height of a gate electrode in a silicidation process includes: a step of piling up a sacrificial cap layer 18 on top of each of one or more gate electrodes 13 to a given height on a semiconductor substrate 10; a step of forming an additional layer 14 of oxide on top of the sacrificial cap layer 18; a step of covering, with a material 17, the semiconductor substrate 10 having the one or more gate electrodes each provided with the sacrificial cap layer 18 on top thereof; a step of performing a planarization process by means of chemical mechanical polishing (CMP); a step of performing a removing process until the sacrificial cap layer 18 on each of the one or more gate electrodes 13 is exposed; and a step of removing the sacrificial cap layer 18 from each of the gate electrodes 13 so that each of the gate electrodes 13 will attain a given height. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在硅化工艺中控制栅电极的高度的方法。 解决方案：在硅化工艺中控制栅电极的高度的方法包括：在半导体衬底上将一个或多个栅电极13中的每一个顶部的牺牲帽层18堆叠到给定高度的步骤 10; 在牺牲盖层18的顶部上形成氧化物附加层14的步骤; 用材料17覆盖具有一个或多个栅电极的半导体衬底10的每个在其顶部上设置有牺牲帽层18的步骤; 通过化学机械抛光（CMP）进行平面化处理的步骤; 进行去除处理的步骤，直到暴露一个或多个栅电极13中的每一个上的牺牲覆盖层18为止; 以及从每个栅电极13去除牺牲帽层18的步骤，使得每个栅电极13将达到给定的高度。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007033454A

公开(公告)日：2007-02-08

申请号：JP2006206778

申请日：2006-07-28

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： FOUCHIER MARC

IPC: G01Q60/24 ,  G01Q60/30 ,  G01Q60/38 ,  G01Q70/10

CPC classification number: G01Q60/30 ,  G01Q70/10

Abstract: PROBLEM TO BE SOLVED: To provide a dual chip AFM probe and a manufacturing method for it having a plurality of electrically insulated chips. SOLUTION: This atomic force microscope probe is constructed of a chip structure 3 having two chips 7 and 8 on a cantilever 2. The probe chips are electrically insulated from each other and have substantially the same height to the cantilever. The surface of the chip structure 3 has an object shaped into a form having a bottom face and an apex. The object is divided into two parts 5 and 6 by a clearance 4 positioned substantially symmetrically to the apex. This invention has relationship to the manufacturing method of this kind of AFM probe. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种双芯片AFM探针及其具有多个电绝缘芯片的制造方法。 解决方案：该原子力显微镜探针由在悬臂2上具有两个芯片7和8的芯片结构3构成。探针芯片彼此电绝缘并且具有与悬臂基本相同的高度。 芯片结构3的表面具有成形为具有底面和顶点的形状的物体。 该物体通过与顶点基本上对称定位的间隙4分成两部分5和6。 本发明与这种AFM探针的制造方法有关。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007005783A

公开(公告)日：2007-01-11

申请号：JP2006146686

申请日：2006-05-26

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： VERHAEGEN GUSTAAF ,  NACKAERTS AXEL

IPC: H01L29/786 ,  B82B3/00 ,  H01L21/336

CPC classification number: H01L21/76281 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/966

Abstract: PROBLEM TO BE SOLVED: To provide a method of high topography patterning which results in a uniform pattern density facilitating the next processing steps and obtains relaxed requirements for active patterning lithography.
SOLUTION: A method of isolating structures of a semiconductor material comprises a step of providing a pattern of the semiconductor material including at least one elevated line; a step of defining device regions which at least include at least one elevated line in the pattern; and a step of modifying the conductive properties of the semiconductor material outside the device regions so as to electrically isolate the device regions.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种高地形图案化的方法，其导致均匀图案密度，促进下一个处理步骤，并获得有源图案化光刻的放松需求。 解决方案：隔离半导体材料的结构的方法包括提供半导体材料的图案的步骤，该图案包括至少一条提升的线; 定义装置区域的步骤，其至少包括图案中的至少一条提升的线; 以及修改器件区域外部的半导体材料的导电性能以使器件区域电隔离的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006173574A

公开(公告)日：2006-06-29

申请号：JP2005299280

申请日：2005-10-13

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： CAYMAX MATTY ,  BONZOM RENAUD ,  LEYS FREDERIK ,  MEURIS MARC

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/16 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/31608 ,  H01L21/31645

Abstract: PROBLEM TO BE SOLVED: To provide a method of inactivating a semiconductor substrate containing semiconductor materials other than silicon in connection with a further IC treatment. SOLUTION: The present method of making an inactivated semiconductor substrate, comprises the steps of: providing a front surface of a mono-crystalline substrate containing the semiconductor materials other than silicon, or consisting of the semiconductor materials other than silicon; and forming a silicon layer on a substrate front surface so that the silicon layer may be substantially lattice matched to a corresponding part of the substrate front surface. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种与进一步的IC处理有关的使含有硅以外的半导体材料的半导体衬底失活的方法。 解决方案：本发明制造半导体半导体衬底的方法包括以下步骤：提供包含除了硅之外的半导体材料或由硅以外的半导体材料构成的单晶衬底的前表面; 以及在衬底前表面上形成硅层，使得硅层可以与衬底前表面的对应部分基本上晶格匹配。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005268794A

公开(公告)日：2005-09-29

申请号：JP2005073084

申请日：2005-03-15

Applicant: Interuniv Micro Electronica Centrum Vzw ,  Koninkl Philips Electronics Nv ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw ,  コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V.

Inventor： DAAMEN ROEL ,  VERHEIJDEN GREJA JOHANNA ADRIA

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a low-cost manufacturing method for a semiconductor device having Damascene structure provided with an air-gap. SOLUTION: The manufacturing method comprises steps of: providing a flat layer M1 including a first metal layer, adhering a route level dielectric material layer VL; processing a pattern of the route level dielectric material layer VL; partially etching the route level dielectric material layer VL; adhering a disposable layer PR on the partially etched route level dielectric material layer VL; processing a pattern of the disposable layer PR; adhering a second metal layer M2, flattening the second metal layer M2; adhering a permeable dielectric material layer PDL after flattening the second metal layer M2; and removing the disposable layer PR through the permeable dielectric material layer PDL in order to form an air gap AG. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为具有设置气隙的具有镶嵌结构的半导体器件提供低成本的制造方法。 解决方案：制造方法包括以下步骤：提供包括第一金属层的平坦层M1，粘附路线层介电材料层VL; 处理路线层介电材料层VL的图案; 部分蚀刻路线层介电材料层VL; 将一次性层PR粘附在部分蚀刻的路线层介电材料层VL上; 处理一次性层PR的图案; 粘附第二金属层M2，使第二金属层M2平坦化; 在使第二金属层M2平坦化之后粘附可渗透介电材料层PDL; 并且通过可渗透介电材料层PDL去除一次性层PR以形成气隙AG。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005268792A

公开(公告)日：2005-09-29

申请号：JP2005071101

申请日：2005-03-14

Applicant: Interuniv Micro Electronica Centrum Vzw ,  Koninkl Philips Electronics Nv ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw ,  コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V.

Inventor： PAWLAK BARTLOMIEJ JAN

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing processing for producing semiconductor substrates and devices on an SOI, while using an SPER technique, such that a single-crystalline silicon layer is produced on an insulator.
SOLUTION: The method of manufacturing a semiconductor device includes a step of providing, on the semiconductor device, a device with a single-crystalline semiconductor layer disposed on an insulating layer. The method is characterized by the following steps providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions; turning the first unshielded portions into amorphous form to form first amorphized portions of the single-crystalline semiconductor layer; injecting first dopant into the first amorphized portions; and applying a first solid phase epitaxial regrowth process to the semiconductor device, while using the first shielded portions as single-crystal seeds.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在SOI上制造半导体衬底和器件的制造工艺，同时使用SPER技术，使得在绝缘体上制造单晶硅层。 解决方案：制造半导体器件的方法包括在半导体器件上提供设置在绝缘层上的单晶半导体层的器件的步骤。 该方法的特征在于以下步骤：在半导体层上提供掩模以提供第一屏蔽部分和第一非屏蔽部分; 将第一非屏蔽部分转变为非晶形式以形成单晶半导体层的第一非晶化部分; 将第一掺杂剂注入第一非晶化部分; 以及在将所述第一屏蔽部分用作单晶种子的同时，向所述半导体器件施加第一固相外延再生长工艺。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005210101A

公开(公告)日：2005-08-04

申请号：JP2004372684

申请日：2004-12-24

Applicant: Infineon Technologies Ag ,  Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： ROSMEULEN MAARTEN

IPC: H01L21/8247 ,  G11C11/34 ,  G11C11/56 ,  G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: B82Y10/00 ,  G11C11/56 ,  G11C13/025 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7923

Abstract: PROBLEM TO BE SOLVED: To provide a high-density flash memory matrix comprising a memory cell capable of storing many bits, the number of which is far larger than two. SOLUTION: A semiconductor device comprises a first contact region 11, a first semiconductor structure 16, a second contact region 12, and a second semiconductor structure 17, wherein the first semiconductor structure 16 and the second semiconductor structure 17 are in electrical contact with each other along an interface, the device comprises means 3 and 4 for modulating the conductivity in at least one of the semiconductor structures, so that the conductivity varies along the interface, in such a way that if current flows across the interface, the current can flow only at a predetermined position 24 along the interface, and the conductivity changes along the interface so that substantially no current can flow at either side of the predetermined position. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高密度闪速存储矩阵，其包括能够存储许多位的存储单元，其数目远远大于2。 解决方案：半导体器件包括第一接触区域11，第一半导体结构16，第二接触区域12和第二半导体结构17，其中第一半导体结构16和第二半导体结构17处于电接触 该装置包括用于调制至少一个半导体结构中的电导率的装置3和4，使得电导率沿着界面变化，使得如果电流流过界面，则电流 沿着界面只能在预定位置24流动，并且电导率沿着界面改变，使得基本上没有电流可以在预定位置的任一侧流动。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005181324A

公开(公告)日：2005-07-07

申请号：JP2004364670

申请日：2004-12-16

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： FOUCHIER MARC

IPC: G01Q30/20 ,  G01Q60/24 ,  G01Q60/38 ,  G01Q70/06 ,  G01Q70/16 ,  G01R1/073 ,  G01N13/16 ,  G12B21/08

CPC classification number: G01Q60/38 ,  Y10T29/42 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: PROBLEM TO BE SOLVED: To provide a method of a probe provided with a moldedly formed tip part prevented from such nonconformity in prior art. SOLUTION: This method for manufacturing the probe for atomic force microscopic examination includes a step of preparing a semiconductor substrate 1, a step for generating a molding die on a surface in one side of the substrate, a step for generating probe structure in the one side, and a step for attaching a holder 6 to a contact areas. A surface of the each contact area is smaller in size than a surface of a holder area attached to the contact area. The method includes further a step for releasing structure including the probe structure and the holder from the substrate, by under-etching the probe structure from a side of substrate generated with the probe structure. The under-etching step is executed subsequent to the step of attaching the holder. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在现有技术中设置有防止这种不整合的模制成形的尖端部分的探针的方法。 解决方案：用于制造原子力显微镜检查用探针的方法包括制备半导体衬底1的步骤，在衬底的一侧的表面上产生模塑模具的步骤，用于产生探针结构的步骤 一侧，以及用于将保持器6附接到接触区域的步骤。 每个接触区域的表面的尺寸小于附接到接触区域的保持器区域的表面。 该方法还包括通过从由探针结构产生的衬底的侧面下蚀刻探针结构，进一步从衬底释放包括探针结构和保持器的结构的步骤。 在附着固定器的步骤之后执行底蚀刻步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005123607A

公开(公告)日：2005-05-12

申请号：JP2004284815

申请日：2004-09-29

Applicant: Interuniv Micro Electronica Centrum Vzw ,  Texas Instr Inc ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw ,  テキサス インスツルメンツ インコーポレイテツド

Inventor： BEYER GERALD ,  GUENEAU DE MUSSY JEAN PAUL ,  MAEX KAREN ,  SUTCLIFFE VICTOR

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To allow selective formation of air gaps in a semiconductor device. SOLUTION: A first dielectric material 1 having contact holes is made of hydrogenated silicon oxycarbide (SiCO:H). By using a UV/ozone treatment including an oxidizer or a process of oxidizing supercritical carbon dioxide or the like, the sidewall of each contact hole is converted into a modified material 4 containing less carbon than the first dielectric material 1. A barrier layer 5 and a copper portion 6 are formed in each contact hole. After that, the modified material 4 is removed by etching using HF to leave an air gap there. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：允许在半导体器件中选择性地形成气隙。 解决方案：具有接触孔的第一介电材料1由氢化硅碳化硅（SiCO：H）制成。 通过使用包括氧化剂或氧化超临界二氧化碳等的UV /臭氧处理，每个接触孔的侧壁被转换成包含比第一电介质材料1少的碳的改性材料4.阻挡层5和 在每个接触孔中形成有铜部分6。 之后，通过使用HF的蚀刻除去改性材料4，以在那里留下气隙。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004132951A

公开(公告)日：2004-04-30

申请号：JP2003163869

申请日：2003-06-09

Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

Inventor： HOLSTEYNS FRANK ,  IACOPI FRANCESCA ,  MAEX KAREN

IPC: G01N23/20 ,  G01N21/47 ,  G01N21/84 ,  G01N21/95 ,  G01N21/956 ,  H01L21/66

CPC classification number: H01L22/24 ,  G01N21/47 ,  G01N21/8422 ,  G01N21/9501 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a detector for detecting a defect in a coating layer of a device. SOLUTION: The present invention relates to an optical method for executing an optical method for detecting the integrity of a material system. This method is provided with optical inspection before and after a solvent absorption step. A underlying layer deposited on a semiconductor substrate is coated based on whether a solvent is absorbed or not, and the existence of the defect, or non-existence thereof is determined in a protection layer for the underlying layer. The method may be used in a processing level, for example, the presence of the defect in the coating layer formed on the semiconductor substrate is determined in manufacture of the electronic device to decide the capability of further processing for the device, or the necessity of removal from the processing. COPYRIGHT: (C)2004,JPO