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    Split and design guideline for double patterning
    1.
    发明专利
    Split and design guideline for double patterning 审中-公开
    分割和设计指南用于双文件

    公开(公告)号：JP2009200499A

    公开(公告)日：2009-09-03

    申请号：JP2009038912

    申请日：2009-02-23

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

    Inventor： WIAUX VINCENT JEAN-MARIE PIERR ,  VERHAEGEN GUSTAAF

    IPC: H01L21/027 ,  G03F1/08

    CPC classification number: G03F7/70475 ,  G03F1/44 ,  G03F1/70

    Abstract: PROBLEM TO BE SOLVED: To provide an excellent method for optimizing a double patterning process used for a lithographic process, and its system. SOLUTION: A method for setting a multiple patterning lithographic process of a pattern in a single layer is disclosed. The multiple patterning lithographic process includes a first patterning step and at least a second patterning step. The method includes, for at least one process condition, obtaining values for at least one metric expressing a splitting correlated process quality as function of design parameters of the pattern and/or split parameters for the multiple patterning lithographic process. The method includes evaluating the values for at least one metric based on the design parameters and the split parameters and considering at least one process condition. The method also includes developing design and/or guidelines for splitting a pattern to be processed using the multiple patterning lithographic process based on the evaluation. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供优化用于光刻工艺的双重图案化工艺及其系统的优良方法。 解决方案：公开了一种用于设置单层图案的多重图形化光刻工艺的方法。 多重图案化平版印刷工艺包括第一图案化步骤和至少第二图案化步骤。 该方法包括对于至少一个处理条件，获得表示分割相关过程质量的至少一个度量的值作为模式的设计参数的函数和/或用于多重图案化平版印刷工艺的分割参数的值。 该方法包括基于设计参数和分割参数评估至少一个度量的值，并考虑至少一个过程条件。 该方法还包括基于评估开发使用多重图案化平版印刷工艺分割待处理图案的设计和/或指南。 版权所有（C）2009，JPO＆INPIT

    Defective etching of germanium
    2.
    发明专利
    Defective etching of germanium 有权
    德国的有缺陷的蚀刻

    公开(公告)号：JP2009182331A

    公开(公告)日：2009-08-13

    申请号：JP2009017681

    申请日：2009-01-29

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

    Inventor： SOURIAU LAURENT ,  TERZIEVA VALENTINA

    IPC: H01L21/308 ,  H01L21/66

    CPC classification number: G01N1/32 ,  C09K13/08 ,  C09K13/12

    Abstract: PROBLEM TO BE SOLVED: To provide an etching solution that exposes defects in a germanium layer, a method that exposes the defects in the germanium layer using such etching solutions, and a method for preparing such solutions.
    SOLUTION: The etching solution contains an oxidant containing Ce
    4
    + or MnO
    4
    - and a solvent and shows an etching rate between 4 nm min
    -1 and 450 nm min
    -1 . This is suitable for exposing the defects in the Ge layer having a film thickness between thin Ge layers, namely, between 20 nm and 10 μm, for example, between 20 nm and 2 μm, between 20 nm and 1 μm, or between 20 nm and 200 nm.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供暴露锗层中的缺陷的蚀刻溶液，使用这种蚀刻溶液暴露锗层中的缺陷的方法，以及制备这种溶液的方法。 解决方案：蚀刻溶液含有含有Ce 3+的氧化剂，或者是含有CeO 4的SBO 4和/或SO 3的溶剂 并且显示出在4nm min -1 <450nm min -1 之间的蚀刻速率。 这适合于在薄Ge层之间，即20nm至10μm之间，例如20nm和2μm之间，20nm至1μm之间或20nm之间的Ge层中的缺陷暴露 和200nm。 版权所有（C）2009，JPO＆INPIT

    Method for making quantum dots
    4.
    发明专利
    Method for making quantum dots 审中-公开
    制造量子的方法

    公开(公告)号：JP2009117829A

    公开(公告)日：2009-05-28

    申请号：JP2008279258

    申请日：2008-10-30

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

    Inventor： ROOYACKERS RITA ,  LEYS FREDERIK ,  NACKAERTS AXEL

    IPC: H01L29/06 ,  H01S5/343

    CPC classification number: H01L29/127 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  Y10S438/962

    Abstract: PROBLEM TO BE SOLVED: To provide a satisfactory method for manufacturing at least one quantum dot in a predetermined position on a substrate, a satisfactory design for a lithographic mask, and a satisfactory method for preparing uch a design. SOLUTION: The method for manufacturing a quantum dot 4 includes a step of forming a semiconductor material layer on the insulating layer of the substrate 1; patterning the semiconductor material layer to form at least one semiconductor material line 2 having a width w L on the substrate 1; and patterning at least one semiconductor material line 2, by a hydrogen annealing to form at least one quantum dot 4 at least at one predetermined position on the substrate 1. At least one semiconductor material line 2 has a local width variation 3, having 20 to 35 nm wide amplitude A, which is wider than the width w L of at least one line of the lines 2, at least at one predetermined position where at least one quantum dot 4 is formed. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在基板上的预定位置制造至少一个量子点的令人满意的方法，用于光刻掩模的令人满意的设计以及用于制备设计的令人满意的方法。 解决方案：量子点4的制造方法包括在基板1的绝缘层上形成半导体材料层的工序; 图案化半导体材料层以在衬底1上形成具有宽度w L 的至少一个半导体材料线2; 并通过氢退火构图至少一个半导体材料线2，以至少在基板1上的一个预定位置处形成至少一个量子点4.至少一个半导体材料线2具有局部宽度变化3，其具有20至 至少在形成有至少一个量子点4的一个预定位置处，宽度为35nm的幅度A比线2的至少一行的宽度w L 宽。 版权所有（C）2009，JPO＆INPIT

    Photon induced etching of copper
    5.
    发明专利
    Photon induced etching of copper 审中-公开
    光电诱发铜的蚀刻

    公开(公告)号：JP2009065124A

    公开(公告)日：2009-03-26

    申请号：JP2008175755

    申请日：2008-07-04

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  Ku Leuven Research & Development ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw ,  カー・イュー・ルーベン・リサーチ・アンド・ディベロップメントK.U.Leuven Research & Development

    Inventor： DICTUS DRIES

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/52

    CPC classification number: H01L21/32136

    Abstract: PROBLEM TO BE SOLVED: To provide a method for removing at least a part of a copper containing layer from a substrate, the substrate including at least a copper containing surface layer.
    SOLUTION: The method includes in a first reaction chamber converting at least a part of the copper containing surface layer 4 into a copper halide surface layer 5 and in a second reaction chamber removing at least a part of the copper halide surface layer 5 by exposing it to a photon atmosphere 6, thereby initiating formation of volatile copper halide products 8. During exposure to the photon atmosphere 6, the method furthermore includes removing the volatile copper halide products 8 from the second reaction chamber to avoid saturation of the volatile copper halide products 8 in the second reaction chamber. The method according to embodiments may be used to pattern copper containing layers. For example, the method according to embodiments may be used to form copper containing interconnect structures in a semiconductor device.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种从基板去除至少一部分含铜层的方法，所述基板至少包括含铜表面层。 解决方案：该方法包括在将含铜表面层4的至少一部分转化为卤化铜表面层5的第一反应室中，并且在第二反应室中除去至少一部分卤化铜表面层5 通过将其暴露于光子气氛6，从而引发挥发性卤化铜产物8的形成。在暴露于光子气体6期间，该方法还包括从第二反应室除去挥发性卤化铜产物8以避免挥发性铜的饱和 第二反应室中的卤化物产物8。 根据实施例的方法可以用于图案化含铜层。 例如，根据实施例的方法可用于在半导体器件中形成含铜互连结构。 版权所有（C）2009，JPO＆INPIT

    Semiconductor device
    6.
    发明专利
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：JP2009038351A

    公开(公告)日：2009-02-19

    申请号：JP2008163159

    申请日：2008-06-23

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

    Inventor： LENOBLE DAMIEN ,  COLLAERT NADINE

    IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/0337 ,  H01L21/26506 ,  H01L29/66795 ,  H01L29/785

    Abstract: PROBLEM TO BE SOLVED: To provide a good method for forming a semiconductor device on a substrate, e.g. a bulk semiconductor substrate or a semiconductor-on-insulator substrate, and to provide a semiconductor device formed by the method.
    SOLUTION: The method includes, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to the plane of a major surface of the substrate, forming locally modified regions 6 at locations in the substrate which are not covered by the at least one structure, thus locally increasing etching resistance of these regions 6. Forming locally modified regions may prevent under-etching of the at least one structure during further process steps in the formation of a semiconductor device 10. Forming locally modified regions 6 may be performed by implanting implantation elements into regions of the substrate not covered by the at least one structure.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供在衬底上形成半导体器件的良好方法，例如， 体半导体衬底或绝缘体上半导体衬底，并提供通过该方法形成的半导体器件。 解决方案：该方法包括在图案化衬底以形成至少一个从衬底延伸的结构，该结构在基本上垂直于衬底的主表面的平面的方向上，在衬底中的位置处形成局部改性区域6， 不被至少一个结构覆盖，从而局部地提高了这些区域6的耐蚀刻性。形成局部改性区域可以防止在形成半导体器件10的进一步工艺步骤期间对至少一种结构的不良蚀刻。在本地形成 修改区域6可以通过将注入元件注入到未被至少一个结构覆盖的衬底的区域中来执​​行。 版权所有（C）2009，JPO＆INPIT

    Method for removing resist layer from substrate
    8.
    发明专利
    Method for removing resist layer from substrate 有权
    从基板去除电阻层的方法

    公开(公告)号：JP2008078658A

    公开(公告)日：2008-04-03

    申请号：JP2007243416

    申请日：2007-09-20

    Applicant: Interuniv Micro Electronica Centrum Vzw ,  アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェInteruniversitair Micro−Elektronica Centrum Vzw

    Inventor： VEREECKE GUY ,  LE QUOC TOAN ,  KESTERS ELS

    IPC: H01L21/027 ,  H01L21/304

    CPC classification number: G03F7/425 ,  G03F7/426 ,  G03F7/428

    Abstract: PROBLEM TO BE SOLVED: To provide a method of removing a resist layer from a substrate easy to be executed and without exerting an influence on a device performance.
    SOLUTION: There is provided a method of removing a resist layer having a bulk resist in contact with a substrate, and a resist skin that exists on an outer surface of the resist layer, including the steps of: at least locally supplying to the resist layer in contact with the substrate a liquid organic solvent which is soluble in the bulk resist and insoluble in the resist skin; supplying a megasonic energy to the organic solvent and dismantling the resist skin, and producing an organic solvent cavitation for dissolving the bulk resist in the organic solvent, thereby peeling-off the resist layer from the substrate.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供从易于执行的基板上去除抗蚀剂层的方法，而不会对器件性能产生影响。 解决方案：提供一种去除具有与基板接触的体抗蚀剂的抗蚀剂层的方法，以及存在于抗蚀剂层的外表面上的抗蚀剂皮肤，包括以下步骤：至少局部供应至 所述抗蚀剂层与所述基底接触，所述液体有机溶剂可溶于所述主体抗蚀剂并且不溶于所述抗蚀剂皮肤; 向有机溶剂提供兆声波能量并拆卸抗蚀剂表皮，并产生用于将体抗蚀剂溶解在有机溶剂中的有机溶剂空穴，从而从基材剥离抗蚀剂层。 版权所有（C）2008，JPO＆INPIT

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