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    Micro sensor
    61.
    发明授权
    Micro sensor 有权

    公开(公告)号：US10539526B2

    公开(公告)日：2020-01-21

    申请号：US15674463

    申请日：2017-08-10

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Sung Hyun Byun

    IPC: G01N27/12

    Abstract: Disclosed is a micro sensor. Particularly, disclosed is a micro sensor capable of changing a resistance value of a resistance unit connected to a sensor electrode depending on a sensing material, the resistance unit having at least two resistors.

    Chip substrate provided with joining grooves in lens insert
    63.
    发明授权
    Chip substrate provided with joining grooves in lens insert 有权

    公开(公告)号：US10128414B2

    公开(公告)日：2018-11-13

    申请号：US14985275

    申请日：2015-12-30

    Applicant: Point Engineering Co., Ltd.

    Inventor： Seung Ho Park ,  Tae Hwan Song

    IPC: H01L33/58 ,  H01L33/48 ,  H01L33/64

    Abstract: A chip substrate includes: a plurality of conductive layers horizontally stacked and constituting the chip substrate; a plurality of insulation layers alternately with the conductive layers and electrically separating the conductive layers; a lens insert comprising a groove having a predetermined number of edges on the upper surface of the chip substrate and having a cross-section wherein an arc is formed at the region where the extended edges meet; a cavity comprising a groove reaching down to a predetermined depth towards the area accommodating the insulation layer within the internal region of the lens insert; and a plurality of joining grooves formed on the surface of the lens insert. Thus, the lens to be inserted also can be formed to be a shape comprising straight lines so that the manufacturing process of the lens to be inserted into the chip substrate can be further simplified.

    Capacitor
    66.
    发明授权
    Capacitor 有权

    公开(公告)号：US09773618B2

    公开(公告)日：2017-09-26

    申请号：US14831964

    申请日：2015-08-21

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Tae Hwan Song

    IPC: H01G4/30 ,  H01G4/12 ,  H01G4/38 ,  H01G4/005 ,  H01G4/012 ,  H01G4/228

    CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01G4/38

    Abstract: The present invention relates to a capacitor. The capacitor includes a substrate; a dielectric layer formed on the substrate; and an electrode layer comprising a first electrode layer and a second electrode layer formed on the dielectric layer, wherein the first electrode layer and the second electrode layer are separated from each other, and at least a portion of the first electrode layer and at least a portion of the second electrode layer are disposed on a same surface. With this configuration, applying the electricity becomes easy, and since the first and the second electrode layers function as the electrodes being charged with different polarity electrical charges respectively, manufacturing thereof becomes easy, and the structure thereof is simple.

    CHIP SUBSTRATE
    68.
    发明申请
    CHIP SUBSTRATE 有权

    公开(公告)号：US20170162754A1

    公开(公告)日：2017-06-08

    申请号：US15363261

    申请日：2016-11-29

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo AHN ,  Seung Ho PARK ,  Tae Hwan SONG

    IPC: H01L33/48

    CPC classification number: H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2924/00014

    Abstract: A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased.

    Chip substrate comprising a groove portion and chip package using the chip substrate
    69.
    发明授权
    Chip substrate comprising a groove portion and chip package using the chip substrate 有权

    公开(公告)号：US09653664B2

    公开(公告)日：2017-05-16

    申请号：US14753915

    申请日：2015-06-29

    Applicant: Point Engineering Co., Ltd.

    Inventor： Sin Seok Han ,  Soo Young Choi ,  Ki Myung Nam

    IPC: H01L29/22 ,  H01L33/58 ,  H01L33/48 ,  H01L33/62 ,  H05K1/03 ,  H05K1/02

    CPC classification number: H01L33/58 ,  H01L33/44 ,  H01L33/486 ,  H01L33/62

    Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent. An existing typical adhesive agent may be used as it is. This provides an effect of saving costs. Thus, there is an advantage in that a low-priced existing bonding material may be applied to a high-priced UV-C (deep-UV) package.

    CHIP SUBSTRATE COMPRISING A PLATED LAYER AND CHIP PACKAGE USING THE SAME
    70.
    发明申请
    CHIP SUBSTRATE COMPRISING A PLATED LAYER AND CHIP PACKAGE USING THE SAME 有权
    包装层的芯片基板和使用其的芯片封装

    公开(公告)号：US20160380159A1

    公开(公告)日：2016-12-29

    申请号：US14753869

    申请日：2015-06-29

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Ki Myung NAM ,  Young Woon JEON ,  Kyoung Ja YUN

    IPC: H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/58

    CPC classification number: H01L33/486 ,  H01L33/44 ,  H01L33/483 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066

    Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.

    Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的不包括空腔的区域的绝缘层，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。

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