公开(公告)号：JPH10284731A

公开(公告)日：1998-10-23

申请号：JP8310798

申请日：1998-03-30

Applicant: ST MICROELECTRON INC

Inventor： MENEGOLI PAOLO

IPC: H01L29/872 ,  H01L27/04 ,  H01L27/07 ,  H01L29/47 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent a parasitizer in the constitution of a DMOS transistor from being activated by forming a Schottky diode, together with a DMOS transistor standing in a row with the main body diode, on the same integrated circuit. SOLUTION: An opening is made by etching through a BPSG oxide layer 96 above an N -drain region 64, N -source regions 90 and 92, a P-region 88, and an epitaxial layer 60. That opening is positioned to expose a P-ring region 88 and a part of the epitaxial layer 60, a P -region 94, and a part of N -source region 90 and 92. Gate electrodes 84 are connected electrically in common by a proper contact, for example, such as a conductive mesh, a second level mutual connector, or the like. Metallic layers 98 and 100 are made, being stuck by a proper technique, suitably by PVD, thus a final DMOS transistor M can be obtained.

公开(公告)号：JPH10284619A

公开(公告)日：1998-10-23

申请号：JP34168497

申请日：1997-12-11

Applicant: ST MICROELECTRON INC

Inventor： HODGES ROBERT L

IPC: G11C11/412 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To enable writing of satisfactory '1' in a memory cell by permitting the memory cell to connect with a first path gate and have a second path gate connected to a complementary bit line and controlling the path gates with a word line and a complementary word line. SOLUTION: This memory cell 102 of a memory 100 includes a line decoder 104, row input/output 106 and a row selection 108 in a matrix. The memory cell 102 is connected with bit lines 110, 112 and word lines 14, 116 by a first path gate 118 and a second path gate 120. The bit line 112 is made a complementary bit line with respect to the bit line 110, and the word line 116 is a complementary word line to the word line 114, and first and second path gates 118 and 120 are controlled by the word line 114 and the complementary word line 116.

公开(公告)号：JPH10271876A

公开(公告)日：1998-10-09

申请号：JP4701398

申请日：1998-02-27

Applicant: ST MICROELECTRON INC

Inventor： CAROBOLANTE FRANCESCO

IPC: H02P6/06 ,  H02P6/08 ,  H02P6/10

Abstract: PROBLEM TO BE SOLVED: To reduce the occurrence of torque ripples by excellently controlling all torques impressed upon a motor and gradually through-processing PWM driving signals during a communication period. SOLUTION: A through-processing type current switch stage 106 generates through-processed control phase signals by using phase control signals from a buffer stage 104, and each of the signals reaches during a transition period and is proportional to its succeeding phase control signal. The through-processed phase signals are through-processed from one state to the next state (for a given phase) with respect to time during the transition period. The through- processed phase control signals are supplied to a comparator 108. The comparator 108 compares the through-processed phase control signals with a triangular wave signal supplied from a triangular wave generator 112 and outputs proportional PWM (pulse width modulation) phase control signals for each phase. Therefore, the occurrence of torque ripples can be reduced.

公开(公告)号：JPH10242290A

公开(公告)日：1998-09-11

申请号：JP35462297

申请日：1997-12-24

Applicant: ST MICROELECTRON INC

Inventor： BLANCHARD RICHARD A ,  CONFALONIERI PIERANGELO

IPC: H01L27/04 ,  G11C5/00 ,  H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/07 ,  H01L29/861 ,  H03K19/0948 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To select one of design options by forming semiconductor layers on a substrate, forming a set of integrated circuit components therein, and selecting one of many modes in response to a signal. SOLUTION: An integrated circuit 10 has a selector 11 and circuit unit 12 which has two series connected resistors R1, R2 and electronic switch SW which is connected in parallel to the resistor R1 and has a control terminal 13. Two different operation states provide two different resistance values of the resistor between terminals 14, 15 of the unit 12. The selector 11 has an inverter 16 having an output terminal 17 connected to the control terminal 3 of the switch SW and input terminal 18 connected to one Vdd.