公开(公告)号：JPH10284619A

公开(公告)日：1998-10-23

申请号：JP34168497

申请日：1997-12-11

Applicant: ST MICROELECTRON INC

Inventor： HODGES ROBERT L

IPC: G11C11/412 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To enable writing of satisfactory '1' in a memory cell by permitting the memory cell to connect with a first path gate and have a second path gate connected to a complementary bit line and controlling the path gates with a word line and a complementary word line. SOLUTION: This memory cell 102 of a memory 100 includes a line decoder 104, row input/output 106 and a row selection 108 in a matrix. The memory cell 102 is connected with bit lines 110, 112 and word lines 14, 116 by a first path gate 118 and a second path gate 120. The bit line 112 is made a complementary bit line with respect to the bit line 110, and the word line 116 is a complementary word line to the word line 114, and first and second path gates 118 and 120 are controlled by the word line 114 and the complementary word line 116.