公开(公告)号：US11876732B2

公开(公告)日：2024-01-16

申请号：US17100505

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Daniel Olson ,  Loic Pallardy ,  Nicolas Anquet

IPC: H04L41/0803 ,  H04L49/109 ,  G06F21/85

CPC classification number: H04L49/109 ,  G06F21/85 ,  H04L41/0803

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.

公开(公告)号：US20240004804A1

公开(公告)日：2024-01-04

申请号：US18346512

申请日：2023-07-03

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Lionel Debieve

IPC: G06F12/14 ,  G06F21/64

CPC classification number: G06F12/1458 ,  G06F21/64

Abstract: The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.

公开(公告)号：US11775037B2

公开(公告)日：2023-10-03

申请号：US17540041

申请日：2021-12-01

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Michael Soulie

IPC: G06F1/24 ,  G06F9/4401 ,  G06F13/40 ,  G06F11/14 ,  G06F15/78

CPC classification number: G06F1/24 ,  G06F9/4401 ,  G06F11/1441 ,  G06F13/4068 ,  G06F15/7807 ,  G06F2213/40

Abstract: The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.

公开(公告)号：US11700174B2

公开(公告)日：2023-07-11

申请号：US16951198

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Nicolas Anquet ,  Loic Pallardy

IPC: H04L41/0803 ,  H04L41/0813 ,  H04L49/109 ,  G06F15/173 ,  G06F15/177 ,  G06F21/85

CPC classification number: H04L41/0813 ,  G06F15/177 ,  G06F15/17306 ,  H04L41/0803 ,  H04L49/109 ,  G06F21/85

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

公开(公告)号：US11630665B2

公开(公告)日：2023-04-18

申请号：US17404835

申请日：2021-08-17

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Lionel Cimaz

IPC: G06F9/22 ,  G06F9/30 ,  H03K5/135

Abstract: A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.

公开(公告)号：US11588353B2

公开(公告)日：2023-02-21

申请号：US17461305

申请日：2021-08-30

Applicant: STMicroelectronics (Grand Ouest) SAS ,  STMicroelectronics S.r.l.

Inventor： Lionel Cimaz ,  Antonio Borrello ,  Simone Ludwig Dalla Stella

IPC: H02J50/12 ,  H04B5/00

Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

公开(公告)号：US20220318392A1

公开(公告)日：2022-10-06

申请号：US17657027

申请日：2022-03-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Franck Albesa ,  Nicolas Anquet

IPC: G06F21/57 ,  G06F21/60 ,  G06F9/4401

Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.

公开(公告)号：US20220209947A1

公开(公告)日：2022-06-30

申请号：US17553481

申请日：2021-12-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Julien COUVRAND ,  William ORLANDO

IPC: H04L9/08

Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

公开(公告)号：US20220147319A1

公开(公告)日：2022-05-12

申请号：US17582748

申请日：2022-01-24

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Frederic Ruelle

IPC: G06F7/58

Abstract: In an embodiment a method for generating a random number includes selecting, by a first object, first symbols from an entropy pool of the first object, wherein the first object is an object of a group of mutually connected objects which are substantially identical, and wherein the entropy pool is fed with second symbols by objects of the group of mutually connected objects, applying, by the first object, a hash function to the first symbols to generate a random seed and generating, by the first object, the random number from the random seed.

公开(公告)号：US11250808B2

公开(公告)日：2022-02-15

申请号：US16858397

申请日：2020-04-24

Applicant: STMicroelectronics (Grand Ouest) SAS ,  STMicroelectronics S.r.l.

Inventor： Alessandro Vittorio Galluzzi ,  Mustapha Ghanmi

IPC: G09G5/00

Abstract: A display system comprises a processing circuit configured to receive image data from a video source, and generate a current image frame by generating pixel data as a function of the image data and storing the pixel data to a frame buffer. A graphic video driver is configured to display the image frame by reading the pixel data from the frame buffer and generating drive signals for the graphic display as a function of the pixel data read. The processing circuit also is configured to insert integrity data into the pixel data of the current image frame, wherein the position of the integrity data within the pixel data changes. The display system comprises a further processing circuit configured to read the pixel data from the frame buffer and verify whether the position of the integrity data within the pixel data changes.