Abstract:
An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.
Abstract:
Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples (30) from a received analog signal at a first sampling rate and identify a first frequency offset of the first stream based on a plurality of parallel correlations (40) using complex reference signals (38) which differ from each other by phase offsets. A second frequency offset is identified (48) based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator. The methods and apparatus may be used in a Bluetooth receiver.
Abstract:
A receiver comprises: means (12) for deriving at least a first stream (30) of first digitized samples from a received analog signal at a first sampling rate, means (40,42) for selecting a first sampling point and at least a second sampling point, a demodulator (44) for demodulating first and second symbols from the at least first stream of samples based on the first and the at least one second sampling points, and means (46) for determining a value related to a demodulation accuracy for the first and second symbols and for outputting a signal, the means (40,42) for selecting being adapted to alter the sampling point based on the signal. By assessing the demodulation accuracy in real time clock drift can be compensated. The demodulation accuracy can be a value related to a phase error or an error energy such as EVM or DEVM for each demodulated symbol.
Abstract:
First and second wireless transceiver units (TX1, TX2) operate in the same portion of the RF spectrum. An arbitration device (130) controls when the first and second wireless transceiver units (TX1, TX2) can operate. An interface (151-154) connects the first transceiver unit (TX1) to the arbitration device (130) and receives requests for operation. The interface permits the transceiver unit (TX1) to use one of N possible priority levels (e.g. N=2) for requests. The transceiver (TX1) associates a transceiver priority level to a series of packets which is chosen from a range of M possible priority levels (where M>N, e.g. M=8). The transceiver unit (TX1) sends a sequence of requests to operate to the arbitration device, each request in the sequence having a priority level chosen from the range of N possible priority levels. The average value of the priority levels used in the sequence depends on the associated transceiver priority level.
Abstract:
An aspect of the present invention is the use of two criteria in channel estimation, e.g. a value related to the length of an estimated Channel Impulse Response ( CIR ) and a value related to a noise content of the received signal, e.g. a Signal-to-Noise Ratio ( SNR ). These parameters can be used for the post-processing algorithm. An advantage of the present invention is that it is much more robust against long channels and/or high noise contents in received signals. Additionally it has moderate implementation complexity.
Abstract:
The present invention is related to a Phase-Locked Loop with multiphase clocks with
a first loop (Main loop) comprising, coupled in cascade, a Phase Frequency Detector (PFD) (1), a Main Charge Pump (2), a Main Loop Filter (3), a Multi-Phase Voltage Controlled Oscillator (VCO) (4) and a Phase-switching Fractional Divider (5), and a second loop (for Calibration) comprising the series connection of a Multiplexer (6) and Y Calibration Loop Filters (7), with Y being an integer, coupled between said Phase Frequency Detector (PFD) (1) and said Multi-Phase Voltage Controlled Oscillator (VCO) (4), said Multiplexer (6) being controlled by a Control Logic (8) coupled to said Phase-Switching Fractional Divider (5), and a Reference Frequency Signal (9) being applied to said Phase Frequency Detector (PFD) (1), characterised in that said Multiplexer (6) has an input connected to an output of said Main Charge Pump (2), and has outputs connected to inputs of said Main Loop Filter (3) and of said Y Calibration Loop Filters (7), and in that a Calibration signal (11) is applied at a control input of said Control Logic (8).