公开(公告)号：EP1753193A1

公开(公告)日：2007-02-14

申请号：EP05447182.6

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro ,  Terryn, Steven ,  Schmit, Jean-Jacques

IPC: H04L27/233

CPC classification number: H04L27/22 ,  H04L7/0041 ,  H04L7/0062 ,  H04L7/007

Abstract: A receiver comprises:
means (12) for deriving at least a first stream (30) of first digitized samples from a received analog signal at a first sampling rate, means (40,42) for selecting a first sampling point and at least a second sampling point,
a demodulator (44) for demodulating first and second symbols from the at least first stream of samples based on the first and the at least one second sampling points, and
means (46) for determining a value related to a demodulation accuracy for the first and second symbols and for outputting a signal, the means (40,42) for selecting being adapted to alter the sampling point based on the signal. By assessing the demodulation accuracy in real time clock drift can be compensated.
The demodulation accuracy can be a value related to a phase error or an error energy such as EVM or DEVM for each demodulated symbol.

Abstract translation: 接收机包括：用于从第一采样率的接收的模拟信号导出第一数字化样本的至少第一流（30）的装置（12），用于选择第一采样点和至少第二采样点的装置（40,42） 采样点，用于基于所述第一和所述至少一个第二采样点从所述至少第一采样流解调第一和第二符号的解调器（44），以及用于确定与所述至少第一采样点相关的解调精度的值 第一和第二符号并且用于输出信号，用于选择的装置（40,42）适于基于该信号改变采样点。 通过评估实时的解调精度，可以补偿时钟漂移。 对于每个解调的符号，解调精度可以是与相位误差或诸如EVM或DEVM的误差能量相关的值。

公开(公告)号：EP1605643A1

公开(公告)日：2005-12-14

申请号：EP04076673.5

申请日：2004-06-07

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H04L12/56 ,  H04L12/28 ,  H04Q7/32

CPC classification number: H04W72/1215 ,  H04W72/1242 ,  H04W74/00 ,  H04W88/06

Abstract: First and second wireless transceiver units (TX1, TX2) operate in the same portion of the RF spectrum. An arbitration device (130) controls when the first and second wireless transceiver units (TX1, TX2) can operate. An interface (151-154) connects the first transceiver unit (TX1) to the arbitration device (130) and receives requests for operation. The interface permits the transceiver unit (TX1) to use one of N possible priority levels (e.g. N=2) for requests. The transceiver (TX1) associates a transceiver priority level to a series of packets which is chosen from a range of M possible priority levels (where M>N, e.g. M=8). The transceiver unit (TX1) sends a sequence of requests to operate to the arbitration device, each request in the sequence having a priority level chosen from the range of N possible priority levels. The average value of the priority levels used in the sequence depends on the associated transceiver priority level.

公开(公告)号：EP1531590A1

公开(公告)日：2005-05-18

申请号：EP03078544.8

申请日：2003-11-11

Applicant: STMicroelectronics Belgium N.V.

Inventor： Wernaers, Yves

IPC: H04L25/02 ,  H04L25/03

CPC classification number: H04L25/0216 ,  H04L25/022 ,  H04L25/0224 ,  H04L25/024 ,  H04L25/03292 ,  H04L2025/03414 ,  H04L2025/03585

Abstract: An aspect of the present invention is the use of two criteria in channel estimation, e.g. a value related to the length of an estimated Channel Impulse Response ( CIR ) and a value related to a noise content of the received signal, e.g. a Signal-to-Noise Ratio ( SNR ). These parameters can be used for the post-processing algorithm. An advantage of the present invention is that it is much more robust against long channels and/or high noise contents in received signals. Additionally it has moderate implementation complexity.

Abstract translation: 本发明的一个方面是在信道估计中使用的两个标准，E.G. 相关的估计信道脉冲响应（CIR）的长度的值和与所接收的信号的噪声内容的值，例如 一个信噪比（SNR）。 这些参数可用于后处理算法。 本发明的一个优点是没有它是对长信道和/或高的噪声内容在接收到的信号更健壮。 此外，它具有适度的实现复杂度。

公开(公告)号：EP1422826A1

公开(公告)日：2004-05-26

申请号：EP02447227.6

申请日：2002-11-21

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

Abstract: The present invention is related to a Phase-Locked Loop with multiphase clocks with

a first loop (Main loop) comprising, coupled in cascade, a Phase Frequency Detector (PFD) (1), a Main Charge Pump (2), a Main Loop Filter (3), a Multi-Phase Voltage Controlled Oscillator (VCO) (4) and a Phase-switching Fractional Divider (5), and
a second loop (for Calibration) comprising the series connection of a Multiplexer (6) and Y Calibration Loop Filters (7), with Y being an integer, coupled between said Phase Frequency Detector (PFD) (1) and said Multi-Phase Voltage Controlled Oscillator (VCO) (4), said Multiplexer (6) being controlled by a Control Logic (8) coupled to said Phase-Switching Fractional Divider (5), and a Reference Frequency Signal (9) being applied to said Phase Frequency Detector (PFD) (1),
characterised in that said Multiplexer (6) has an input connected to an output of said Main Charge Pump (2), and has outputs connected to inputs of said Main Loop Filter (3) and of said Y Calibration Loop Filters (7),
and in that a Calibration signal (11) is applied at a control input of said Control Logic (8).

Abstract translation: 本发明涉及具有多相时钟的锁相环，具有第一回路（主回路），其包括级联耦合的相位检波器（PFD）（1），主电荷泵（2），主回路 滤波器（3），多相电压控制振荡器（VCO）（4）和相位切换分数分频器（5），以及第二回路（用于校准），包括多路复用器（6）和Y校准 环路滤波器（7），其中Y是整数，耦合在所述相位频率检测器（PFD）（1）和所述多相压控振荡器（VCO）（4）之间，所述多路复用器（6）由控制逻辑 （8）耦合到所述相位切换分数分频器（5），以及参考频率信号（9），其被施加到所述相位频率检测器（PFD）（1），其特征在于，所述多路复用器（6）具有连接到 所述主电荷泵（2）的输出，并且具有连接到所述主回路滤波器（3）和所述Y卡利 （7），并且在所述控制逻辑（8）的控制输入处施加校准信号（11）。