公开(公告)号：WO2017188718A1

公开(公告)日：2017-11-02

申请号：PCT/KR2017/004417

申请日：2017-04-26

Applicant: SEOUL VIOSYS CO., LTD. ,  SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SIMIN, Grigory ,  SHUR, Michael ,  DOBRINSKY, Alexander

IPC: H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L27/105

CPC classification number: H05B33/0809 ,  H01L25/167 ,  H01L27/15 ,  H01L33/60 ,  H05B33/0845

Abstract: A solid-state light source (SSLS) with an integrated electronic modulator is described. A device can include a SSLS having an active p-n junction region is formed within the SSLS for electron-hole pair recombination and light emission the active p-n junction region can include a n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A pair of current supply electrodes can be formed to receive a drive current from a current supply source that drives the SSLS. A field-effect transistor (FET) modulator can be monolithically integrated with the SSLS for modulation thereof. The FET modulator can receive a modulation voltage from a modulation voltage source. The modulation voltage includes voltage pulses having a pulse amplitude and polarity to turn on and off current flowing through the FET modulator. These voltage pulses enable the FET modulator to control the drive current supplied to the SSLS.

Abstract translation: 描述了具有集成电子调制器的固态光源（SSLS）。 器件可以包括具有有源pn结区的SSLS形成在SSLS内用于电子 - 空穴对复合和发光，有源pn结区可以包括n型半导体层，p型半导体层和产生光 结构之间形成结构。 可以形成一对电流供应电极以接收来自驱动SSLS的电流源的驱动电流。 场效应晶体管（FET）调制器可以与SSLS单片集成以对其进行调制。 FET调制器可以从调制电压源接收调制电压。 调制电压包括具有脉冲振幅和极性的电压脉冲，以导通和关断流过FET调制器的电流。 这些电压脉冲使FET调制器能够控制提供给SSLS的驱动电流。

公开(公告)号：WO2017136509A1

公开(公告)日：2017-08-10

申请号：PCT/US2017/016148

申请日：2017-02-02

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC. ,  SEOUL VIOSYS CO., LTD.

Inventor： BETTLES, Timothy, James ,  SHUR, Michael ,  DOBRINSKY, Alexander ,  SHATALOV, Maxim, S.

IPC: B29C35/08 ,  B29C35/00

CPC classification number: C09D5/32 ,  B05D3/067 ,  C08J7/123 ,  C09D11/101 ,  C09D201/00 ,  C09J9/00 ,  C09J201/00 ,  G21K5/02

Abstract: An approach for curing ultraviolet sensitive polymer materials (e.g., polymer inks, coatings, and adhesives) using ultraviolet radiation is disclosed. The ultraviolet sensitive polymer materials curing can utilize ultraviolet light at different wavelength emissions arranged in a random, mixed or sequential arrangement. In one embodiment, an ultraviolet light C (UV-C) radiation emitter having a set of UV-C sources that emit UV-C radiation at a predetermined UV-C duration and intensity operate in conjunction with an ultraviolet light B (UV-B) radiation emitter having a set of UV-B sources configured to emit UV-B radiation at a predetermined UV-B duration and intensity and/or an ultraviolet light A (UV-A) radiation emitter having a set of UV-A sources configured to emit UV-A radiation at a predetermined UV-A duration and intensity, to cure the ultraviolet sensitive polymer materials.

Abstract translation: 公开了一种使用紫外辐射固化紫外线敏感聚合物材料（例如聚合物油墨，涂料和粘合剂）的方法。 紫外线敏感聚合物材料固化可以利用以随机，混合或顺序布置排列的不同波长发射的紫外光。 在一个实施例中，具有以预定的UV-C持续时间和强度发射UV-C辐射的一组UV-C源的紫外光C（UV-C）辐射发射器与紫外光B（UV-B ）辐射发射器，其具有配置成以预定的UV-B持续时间和强度发射UV-B辐射的一组UV-B辐射源和/或具有配置的一组UV-A辐射源的紫外光A（UV-A）辐射发射器 以预定的UV-A持续时间和强度发射UV-A辐射，以固化紫外线敏感聚合物材料。

公开(公告)号：WO2017048735A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/051564

申请日：2016-09-14

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SIMIN, Grigory ,  SHUR, Michael

IPC: H01L33/00 ,  H01L33/02 ,  H01L29/78 ,  H01L33/38 ,  H01L33/22

CPC classification number: H01L27/0266 ,  H01L23/62 ,  H01L25/167 ,  H01L27/0248

Abstract: A solid-state light source (SSLS) with an integrated short-circuit protection approach is described. A device can include a SSLS having an n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A field-effect transistor (FET) can be monolithically connected in series with the SSLS. The FET can have a saturation current that is greater than the normal operating current of the SSLS and less than a predetermined protection current threshold specified to protect the SSLS and the FET.

Abstract translation: 描述了具有集成短路保护方法的固态光源（SSLS）。 器件可以包括具有n型半导体层的SSLS，p型半导体层和在其间形成的发光结构。 场效应晶体管（FET）可以与SSLS串联单片连接。 FET可以具有大于SSLS的正常工作电流的饱和电流，并且小于为保护SSLS和FET而规定的预定保护电流阈值。

公开(公告)号：WO2017004497A1

公开(公告)日：2017-01-05

申请号：PCT/US2016/040656

申请日：2016-07-01

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SHUR, Michael ,  DOBRINSKY, Alexander ,  SHATALOV, Maxim, S.

IPC: H01L21/768 ,  H01L21/268 ,  H01L21/20

CPC classification number: H01L33/0079 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/304 ,  H01L21/30612 ,  H01L21/6835 ,  H01L21/7813 ,  H01L33/007 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

Abstract translation: 描述了用于光电子器件的诸如III族氮化物异质结构的异质结构的制造。 异质结构可以在位于衬底结构上的牺牲层上外延生长。 牺牲层可以使用激光至少部分分解。 衬底结构可以从异质结构完全去除或保持附着于其上。 可以使用用于将衬底结构从异质结构分离的一种或多种另外的解决方案。 异质结构可经历附加处理以形成光电器件。

公开(公告)号：WO2015127399A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/017161

申请日：2015-02-23

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SHATALOV, Maxim, S. ,  YANG, Jinwei ,  DOBRINSKY, Alexander ,  SHUR, Michael ,  GASKA, Remigijus

IPC: H01L33/12

CPC classification number: H01L33/12 ,  G06F17/505 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/145 ,  H01L33/24 ,  H01L33/32 ,  H01L33/38 ,  H01L33/46

Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

Abstract translation: 提供一种半导体结构，包括缓冲结构和与缓冲结构的第一侧相邻形成的一组半导体层。 缓冲结构可以具有有效的晶格常数和厚度，使得该组半导体层在室温下的总应力是压缩的并且在约0.1GPa和2.0GPa之间的范围内。 可以使用选择的一组生长参数来生长缓冲结构，以实现目标有效晶格常数a，缓冲结构生长期间存在的控制应力和/或半导体结构冷却后存在的控制应力。

公开(公告)号：WO2015061325A1

公开(公告)日：2015-04-30

申请号：PCT/US2014/061586

申请日：2014-10-21

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SHATALOV, Maxim, S. ,  JAIN, Rakesh ,  YANG, Jinwei ,  DOBRINSKY, Alexander ,  SHUR, Michael ,  GASKA, Remigijus

IPC: H01L27/10 ,  H01L27/04

CPC classification number: H01L29/151 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0075 ,  H01L33/12

Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

Abstract translation: 提供了用于电子或光电子器件的异质结构。 异质结构包括一个或多个复合半导体层。 复合半导体层可以包括不同形态的子层，其中至少一个可以由一组柱状结构（例如，纳米线）形成。 复合半导体层中的另一个子层可以是多孔的，连续的或部分连续的。

公开(公告)号：WO2015051051A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/058712

申请日：2014-10-02

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SHUR, Michael ,  SHATALOV, Maxim, S. ,  DOBRINSKY, Alexander ,  GASKA, Remigijus

IPC: H01L33/30

CPC classification number: H01L33/12 ,  H01L33/007 ,  H01L33/145 ,  H01L33/32 ,  H01L33/382 ,  H01L33/387 ,  H01L33/405 ,  H01L33/42 ,  H01L33/44 ,  H01L2933/0016 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can be located between a semiconductor layer and another layer of material. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor layer. The layer of material can penetrate at least some of the plurality of pores and directly contact the semiconductor layer. In an illustrative embodiment, the layer of material is a conductive material and the anodic aluminum oxide is located at a p-type contact.

Abstract translation: 描述了包括阳极氧化铝层的半导体结构。 阳极氧化铝层可以位于半导体层和另一层材料之间。 阳极氧化铝层可以包括延伸到半导体层的相邻表面的多个孔。 材料层可以穿透多个孔中的至少一些并直接接触半导体层。 在说明性实施例中，材料层是导电材料，阳极氧化铝位于p型接触处。

公开(公告)号：WO2014179523A2

公开(公告)日：2014-11-06

申请号：PCT/US2014/036291

申请日：2014-05-01

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SHATALOV, Maxim, S. ,  YANG, Jinwei ,  SUN, Wenhong ,  JAIN, Rakesh ,  SHUR, Michael ,  GASKA, Remigijus

CPC classification number: H01L29/158 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。

公开(公告)号：WO2014110197A1

公开(公告)日：2014-07-17

申请号：PCT/US2014/010772

申请日：2014-01-09

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： GASKA, Remigijus ,  SHATALOV, Maxim, S. ,  LUNEV, Alex ,  DOBRINSKY, Alexander ,  YANG, Jinwei ,  SHUR, Michael

IPC: H01L33/40

CPC classification number: H01L33/22 ,  H01L24/05 ,  H01L24/14 ,  H01L33/32 ,  H01L33/38 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/1134 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2924/00

Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

Abstract translation: 公开了一种包括第一半导体层和与第一半导体层的接触的器件。 第一半导体层和触点之间的界面包括具有特征高度和特征宽度的第一粗糙度轮廓。 特征高度可以对应于第一粗糙度轮廓中波峰和相邻谷之间的平均垂直距离。 特征宽度可以对应于第一粗糙度轮廓中的波峰和相邻谷之间的平均横向距离。

公开(公告)号：WO2014052948A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/062540

申请日：2013-09-30

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： SIMIN, Grigory ,  SHUR, Michael ,  GASKA, Remigijus

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/408 ,  G06F17/5068 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/872

Abstract: A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high- voltage surface region during operation of the device into multiple much smaller spikes.

Abstract translation: 提供具有防分解层的半导体器件。 防破坏层可以位于器件的高压表面区域中。 防破坏层可以包括其中嵌入有导电元件的绝缘膜。 导电元件可以沿绝缘膜的横向长度布置。 导电元件可以被配置为在设备操作期间将高电场尖峰分开，否则存在于高压表面区域中，以形成多个更小的尖峰。