公开(公告)号：KR1020020074667A

公开(公告)日：2002-10-04

申请号：KR1020010014590

申请日：2001-03-21

Applicant: 삼성전자주식회사

Inventor： 정무경 ,  안종현

IPC: H01L21/336

Abstract: PURPOSE: A method for forming a gate electrode of a semiconductor device is provided to easily achieve a stable gate structure having constantly vertical shape irrespective of quantity of implanted dopants. CONSTITUTION: After forming a gate oxide(112a) on a semiconductor substrate(110), an undoped gate electrode(114a) made of polysilicon is formed on the gate oxide. The first and the second photoresist layer(116,118) are sequentially coated on the undoped gate electrode. The second photoresist layer(118) is then etched, wherein the etched width of the second photoresist layer(118) is wider than that of the undoped gate electrode(114a). Impurity ions are implanted into the undoped gate electrode(114a) by using the second photoresist pattern as a mask.

Abstract translation: 目的：提供一种用于形成半导体器件的栅极的方法，以便容易地实现具有恒定垂直形状的稳定的栅极结构，而与注入的掺杂剂的量无关。 构成：在半导体衬底（110）上形成栅极氧化物（112a）之后，在栅极氧化物上形成由多晶硅制成的未掺杂的栅电极（114a）。 第一和第二光致抗蚀剂层（116,118）依次涂覆在未掺杂的栅电极上。 然后蚀刻第二光致抗蚀剂层（118），其中第二光致抗蚀剂层（118）的蚀刻宽度比未掺杂的栅电极（114a）的蚀刻宽度宽。 通过使用第二光致抗蚀剂图案作为掩模将杂质离子注入到未掺杂的栅电极（114a）中。

公开(公告)号：KR1020000013506A

公开(公告)日：2000-03-06

申请号：KR1019980032397

申请日：1998-08-10

Applicant: 삼성전자주식회사

Inventor： 정무경 ,  김영욱 ,  도명근

IPC: H01L21/28

Abstract: PURPOSE: Insulating substance with a constant mutation is lead in to solve the problem that the increase of a parasitic capacitance and resistance of metal wiring widens and a gap of metal wiring decrease. And to solve the problem of contact errors or etc., when a profile forms multiple wiring structure on the metal pattern due to difference of the applied thickness of metal substance and when the use of a low dielectric film as an insulating substance of metal patterns of various dimension. CONSTITUTION: After stacking the metal wiring layer(110) on a substrate(100) insulating layer for blocking etching(120) is stacked, the insulating layer for blocking etching (120) and the metal wiring layer(110) are patterned. A low dielectric film(130a) is stacked between the metal patterns and flatting process is performed to the front surface of the insulating film for blocking etching (120) using CMP(Chemical Mechanical Polishing). Thus contact errors caused by profile difference of the low dielectric film is avoided in manufacturing semiconductor device forming metal patterns with various dimension on a plane.

Abstract translation: 目的：不断变形的绝缘物质导致了寄生电容增加和金属布线电阻增大，金属布线间隙减小的问题。 为了解决接触错误等的问题，当由于金属物质的施加厚度的差异而在金属图案上形成多个布线结构时，并且当使用低介电膜作为金属图案的绝缘物质时 各种维度。 构成：堆叠金属布线层（110）叠层在基板（100）绝缘层（120）上时，图案化用于阻挡蚀刻的绝缘层（120）和金属布线层（110）。 在金属图案之间层叠低电介质膜（130a），使用CMP（Chemical Mechanical Polishing，化学机械抛光）对绝缘膜的绝缘膜（120）的前表面进行平坦化处理。 因此，在制造在平面上形成各种尺寸的金属图案的半导体器件中，避免了由低介电膜的轮廓差引起的接触误差。