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公开(公告)号：KR101350388B1
公开(公告)日：2014-01-15
申请号：KR1020120132977
申请日：2012-11-22
Applicant: 숭실대학교산학협력단
CPC classification number: H01L25/0657 , G05F3/16 , H01L2924/0002 , H01L2924/00
Abstract: The present invention relates to an integrated circuit having a stack structure. According to the present invention, provided is an integrated circuit having a stack structure, comprising: a first integrated circuit of which a power supply voltage is applied to a power input terminal; and a second integrated circuit of which a power input terminal is connected to a ground terminal of the first integrated circuit, of which voltage is applied to a central node formed by the connection, and of which a ground terminal is connected to a ground power supply voltage, wherein the power supply voltage is divided into first and second voltages to be each supplied to the first and second integrated circuits. The integrated circuit having a stack structure can connect the integrated circuits with the stack structure to reduce the number of pads and operate the integrated circuits at a high power supply voltage. In addition, the integrated circuit can reduce the number of pads to lower production costs and can operate the integrated circuits at a low power supply voltage even though a high power supply voltage is applied to reduce power consumption.
Abstract translation: 本发明涉及具有堆叠结构的集成电路。 根据本发明，提供一种具有堆叠结构的集成电路，包括：第一集成电路，其电源电压施加到电力输入端; 以及第二集成电路，其电源输入端子连接到所述第一集成电路的接地端子，所述第一集成电路的电压被施加到由所述连接形成的中心节点，并且其接地端子连接到地电源 电压，其中电源电压被分成要被提供给第一和第二集成电路的第一和第二电压。 具有堆叠结构的集成电路可以将集成电路与堆叠结构连接，以减少焊盘的数量并在高电源电压下操作集成电路。 此外，即使施加高电源电压以降低功耗，集成电路可以减少焊盘的数量以降低生产成本并且可以以低电源电压操作集成电路。
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公开(公告)号：KR101338015B1
公开(公告)日：2013-12-09
申请号：KR1020120082535
申请日：2012-07-27
Applicant: 숭실대학교산학협력단
CPC classification number: H03F3/211 , H03F1/0283 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/3022 , H03F3/3028 , H03F3/45179 , H03F3/45237 , H03F2200/405 , H03F2200/408 , H03F2200/516 , H03F2203/45481 , H03F2203/45544 , H03F2203/45594 , H03F2203/45631
Abstract: The present invention relates to a power amplifier which has a stack structure. The power amplifier includes: a first driving amplifier stage in which a power supply voltage is applied from a power source and which receives and amplifies an input signal; a second driving amplifier stage in which a virtual grounding voltage is applied by being connected to the grounding stage of the first driving amplifier stage at a power input stage and which receives and amplifies the output signal of the first driving amplifier stage by being connected to the output stage of the first driving amplifier stage at the input stage; and power amplifier stage in which the power supply voltage is applied from the power source and which receives and amplifies the output signal of the second driving amplifier stage by being connected to the output stage of the second driving amplifier stage at the input stage. According to the forementioned, the power amplifier is able to reduce the number of regulators which supply the power supply voltage and also reduce the designed area of an integrated circuit by connecting multiple driving amplifier stages which comprise a multi-stage amplifier in the stack structure. [Reference numerals] (AA) Input;(BB) Output
Abstract translation: 本发明涉及具有堆叠结构的功率放大器。 功率放大器包括：第一驱动放大器级，其中从电源施加电源电压并且其接收和放大输入信号; 第二驱动放大级，其中通过在功率输入级连接到第一驱动放大器级的接地级并且通过连接到第一驱动放大器级的输出信号来接收和放大第一驱动放大器级的输出信号来施加虚拟接地电压 在输入级的第一驱动放大器级的输出级; 以及功率放大级，其中从电源施加电源电压，并且通过在输入级连接到第二驱动放大器级的输出级来接收和放大第二驱动放大器级的输出信号。 根据前述，功率放大器能够减少提供电源电压的调节器的数量，并且还通过在堆叠结构中连接包括多级放大器的多个驱动放大器级来减小集成电路的设计面积。 （标号）（AA）输入;（BB）输出
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公开(公告)号：KR101338711B1
公开(公告)日：2013-12-06
申请号：KR1020120059946
申请日：2012-06-04
Applicant: 숭실대학교산학협력단
CPC classification number: H03F1/223 , H03F1/0211 , H03F3/191 , H03F2203/21127
Abstract: The present invention relates to a power amplifying device using a current source. The power amplifying device according to an embodiment of the invention includes a common source transistor having a gate connected to an input node, a power amplifier connected with the transistor in a cascode type and including a common gate transistor having a drain connected to an output node, and a current source connected to a source of the common source transistor and supplying a changeable current to the power amplifier. According to this, a range of output power of the power amplifier is improved by changing a current flowing through the power amplifier by connecting the changeable current with the power amplifier.
Abstract translation: 本发明涉及一种使用电流源的功率放大装置。 根据本发明的实施例的功率放大装置包括具有连接到输入节点的栅极的公共源晶体管，与共晶共栅型晶体管连接的功率放大器，并且包括公共栅极晶体管，漏极连接到输出节点 以及电流源，连接到所述公共源晶体管的源极，并向所述功率放大器提供可变电流。 据此，通过将可变电流与功率放大器连接来改变流过功率放大器的电流，能够提高功率放大器的输出功率范围。
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公开(公告)号：KR101332569B1
公开(公告)日：2013-11-25
申请号：KR1020120131846
申请日：2012-11-20
Applicant: 숭실대학교산학협력단
Abstract: The present invention relates to a differential multistage distributed amplifier, a differential multistage distributed amplifier according to the embodiment of the present invention includes: a first multistage distributed amplification stage including a first input stage, a plurality of first inductors serially connected to the first input stage and a plurality of first transistors for receiving a first differential signal, for amplifying the signal and for outputting the amplified first differential signal through a drain by connecting a gate at a contact point with the first inductor; and a second multistage distributed amplification stage including a second input stage, a plurality of second inductors serially connected to the second input stage and a plurality of second transistors for receiving a second differential signal of which phase is the opposite to the first differential signal, for amplifying the signal and for outputting the amplified second differential signal through a drain by connecting a gate at a contact point with the second inductor. According to input intensity of the multistage amplifier, the amplification mode is automatically converte and the amplification efficiency is able to be increased. Furthermore, the area of a circuit is able to be reduced by using a differential inductor when designing a circuit.
Abstract translation: 本发明涉及一种根据本发明实施例的差分多级分布式放大器，差分多级分布式放大器，包括：第一多级分布放大级，包括第一输入级，串联连接到第一输入级的多个第一电感 以及多个第一晶体管，用于接收第一差分信号，用于放大信号并通过连接与第一电感器的接触点处的栅极通过漏极输出放大的第一差分信号; 以及第二多级分布放大级，包括第二输入级，串联连接到第二输入级的多个第二电感器和用于接收与第一差分信号相反的相位的第二差分信号的多个第二晶体管，用于 通过在与第二电感器的接触点处连接栅极，放大信号并通过漏极输出放大的第二差分信号。 根据多级放大器的输入强度，放大模式自动转换，放大效率可以提高。 此外，在设计电路时，可以通过使用差分电感来减小电路的面积。
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公开(公告)号：KR101322738B1
公开(公告)日：2013-11-04
申请号：KR1020120126359
申请日：2012-11-08
Applicant: 숭실대학교산학협력단
IPC: H02M7/155
CPC classification number: H03K19/018521
Abstract: The present invention relates to a power amplifier using a differential structure. The power amplifier using the differential structure according to the present invention comprises: first and second transistors in which each first end is connected to a first power source supplying a first voltage and signals having the same size and different polarities are inputted; third and fourth transistors in which each first end is connected to the first ends of the first and second transistors; and a fifth transistor in which a first end is connected to second ends of the third and fourth transistors. The fifth transistor controls the oscillation of the third or fourth transistor. The power amplifier using the differential structure according to the present invention can reduce driving electricity which is necessary for a power amplifier end by using a help transistor and produce a large output. The power amplifier using the differential structure forms a switch transistor with a small size by connecting the switch transistor for controlling the oscillation only to the help transistor which becomes the cause of the oscillation and obtains an economic effect of reducing manufacturing costs.
Abstract translation: 本发明涉及一种使用差分结构的功率放大器。 使用根据本发明的差分结构的功率放大器包括：第一和第二晶体管，其中每个第一端连接到提供第一电压的第一电源，并输入具有相同尺寸和不同极性的信号; 第三和第四晶体管，其中每个第一端连接到第一和第二晶体管的第一端; 以及第五晶体管，其中第一端连接到第三和第四晶体管的第二端。 第五晶体管控制第三或第四晶体管的振荡。 使用根据本发明的差分结构的功率放大器可以通过使用帮助晶体管来减少功率放大器端所需的驱动电力并产生大的输出。 使用差分结构的功率放大器通过将用于控制振荡的开关晶体管连接到成为振荡原因的帮助晶体管而形成具有小尺寸的开关晶体管，并获得降低制造成本的经济效果。
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Patent Agency Ranking
公开(公告)号：KR101262643B1
公开(公告)日：2013-05-08
申请号：KR1020110105892
申请日：2011-10-17
Applicant: 숭실대학교산학협력단
IPC: H01L27/085 , H01L29/78 , H01L21/336
CPC classification number: H01L27/088 , H01L27/0207
Abstract: 본발명은멀티트랜지스터및 그제조방법에관한것으로, 본발명의일 실시예에따른멀티트랜지스터는, 게이트와, 상기게이트의일 측에형성되는제1 소스와, 상기게이트의타 측에형성되는제1 드레인을포함하는제1 트랜지스터와, 상기기판에상기제1 소스와대향하여상기게이트의일 측에형성되는제2 드레인과, 상기제1 드레인과대향하여상기게이트의타 측에형성되는제2 소스를포함하는제2 트랜지스터를포함함으로써, 대향하는트랜지스터에서발생하는기생인덕턴스성분을최소화할수 있다.
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公开(公告)号：KR1020130025131A
公开(公告)日：2013-03-11
申请号：KR1020110088483
申请日：2011-09-01
Applicant: 숭실대학교산학협력단
CPC classification number: H01L21/4867 , G01R31/2822 , G01R31/3025 , H01L23/66 , H01L25/0657 , H01L2224/16145 , H01L2224/48091 , H01L2224/49113 , H01L2225/0651 , H01L2225/06531 , H01L2225/06565 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A wireless integrated circuit package, a manufacturing method thereof, and a wireless integrated circuit test device are provided to constantly maintain an interval between wireless integrated circuits by laminating the wireless integrated circuits using a spacer. CONSTITUTION: A plurality of wireless integrated circuits(220) are laminated on a substrate. A spacer(230) is located between a plurality wireless integrated circuits. The wireless integrated circuits include an integrated circuit, a wireless communication pad(222), and a protection layer(223). A wireless communication pad is formed on the integrated circuit. A protection layer is formed on the integrated circuit and the wireless communication pad. A connection pad(224) connected to a signal line with a bonding wire is formed on one wireless integrated circuit.
Abstract translation: 目的：提供一种无线集成电路封装，其制造方法和无线集成电路测试装置，以通过使用间隔件层叠无线集成电路来不间断地保持无线集成电路之间的间隔。 构成：将多个无线集成电路（220）层叠在基板上。 间隔物（230）位于多个无线集成电路之间。 无线集成电路包括集成电路，无线通信焊盘（222）和保护层（223）。 在集成电路上形成无线通信焊盘。 在集成电路和无线通信垫上形成保护层。 在一个无线集成电路上形成连接到具有接合线的信号线的连接焊盘（224）。
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公开(公告)号：KR1020120103008A
公开(公告)日：2012-09-19
申请号：KR1020110020984
申请日：2011-03-09
Applicant: 숭실대학교산학협력단
IPC: G02F1/1333 , G02F1/1345 , G06F1/16 , H04B1/38
CPC classification number: G06F1/16 , G02F1/1333 , G02F1/1345 , H04B1/38
Abstract: PURPOSE: A display terminal device with an RF circuit is provided to directly form a passive element on a portion of a display screen, thereby reducing production costs. CONSTITUTION: A display substrate(440) is formed by a semiconductor manufacturing process. A passive element(420) is formed on the display substrate. A high frequency integrated circuit(430) is arranged on the outside of the display substrate. The high frequency integrated circuit is connected to the passive element. The passive element is connected to the high frequency integrated circuit by a bonder and a wire.
Abstract translation: 目的：提供具有RF电路的显示终端装置，以在显示屏的一部分上直接形成无源元件，从而降低生产成本。 构成：通过半导体制造工艺形成显示基板（440）。 无源元件（420）形成在显示器基板上。 高频集成电路（430）布置在显示基板的外侧。 高频集成电路连接到无源元件。 无源元件通过接合器和导线连接到高频集成电路。
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公开(公告)号：KR101167454B1
公开(公告)日：2012-07-26
申请号：KR1020110027508
申请日：2011-03-28
Applicant: 숭실대학교산학협력단
CPC classification number: H03F3/45179 , H03F3/21 , H03F3/45183 , H03F2203/45034 , H03F2203/45318 , H03F2203/45352 , H03F2203/45481 , H03F2203/45638
Abstract: PURPOSE: A power amplifier using a differential structure is provided to save necessary driving power in a power amplifier stage by using a help transistor. CONSTITUTION: A power amplifier using a differential structure includes first and second inductors(201,202) and first to fifth transistors(210,220,230,240,250). The power amplifier amplifies a voltage difference between two input signals applied to both ends of the first and second transistors. The third and fourth transistors corresponding to a help transistor help to amplify output from the power amplifier. A fifth transistor(250) corresponding to a switch transistor prevents the oscillation of the power amplifier by controlling the operation of the third and fourth transistors.
Abstract translation: 目的：提供使用差分结构的功率放大器，通过使用帮助晶体管在功率放大器级中节省必要的驱动功率。 构成：使用差分结构的功率放大器包括第一和第二电感器（201,202）和第一至第五晶体管（210,220,230,240,250）。 功率放大器放大施加到第一和第二晶体管两端的两个输入信号之间的电压差。 对应于帮助晶体管的第三和第四晶体管有助于放大来自功率放大器的输出。 对应于开关晶体管的第五晶体管（250）通过控制第三和第四晶体管的操作来防止功率放大器的振荡。
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公开(公告)号：KR101094274B1
公开(公告)日：2011-12-19
申请号：KR1020090120732
申请日：2009-12-07
Applicant: 숭실대학교산학협력단
Inventor： 박창근
Abstract: 본 발명은 변압기를 이용하여 모드-주입(Mode-locking) 기법을 적용한 전력 증폭기에 관한 것으로서, 보다 자세하게는 차동 구조로 된 전력 증폭기 구조에 있어서, 모드-주입을 위하여 추가 되는 트랜지스터의 게이트는 전송선 변압기를 통하여 기존 트랜지스터의 드레인으로 부터 전력을 공급받는 전력 증폭기에 관한 것이다. 본 발명에 의하면, 기존 트랜지스터의 드레인과 모드-주입을 위하여 추가 되는 트랜지스터의 게이트는 DC 적으로 분리 되어 있기 때문에, 기존 트랜지스터의 드레인 전압과, 모드-주입을 위하여 추가된 트랜지스터의 게이트 전압을 용이하게 분리 가능하다.
반도체 집적회로, 고주파, 변압기, 전송선, 모드-주입(Mode-Locking)
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