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公开(公告)号：WO2013035933A1
公开(公告)日：2013-03-14
申请号：PCT/KR2011/008408
申请日：2011-11-07
Applicant: 숭실대학교산학협력단 , 강병주 , 안성훈 , 황호용 , 박창근
CPC classification number: H01F27/2804 , H01F27/40 , H01F2027/2814 , H05K1/165 , H05K3/222 , H05K2203/049
Abstract: 본 발명은 변압기에 관한 것으로, 본 발명의 일 실시예에 따른 대칭형 인쇄 패턴을 이용한 변압기는 기판과, 상기 기판에 서로 이격되어 인쇄되는 복수의 제1 인쇄선과, 상기 기판에 서로 이격되어 인쇄되는 복수의 제2 인쇄선과, 상기 복수의 제1 인쇄선들을 서로 연결하는 제1 본딩 와이어와, 상기 복수의 제2 인쇄선들을 서로 연결하는 제2 본딩 와이어를 포함하며, 상기 제1 인쇄선과 상기 제2 인쇄선은 각각 대칭적인 인쇄 패턴으로 상기 기판에 인쇄되고, 상기 제1 본딩 와이어와 상기 제2 본딩 와이어는 각각 대칭적으로 형성된다. 이에 따라, 변압기와 연결되는 대칭형 소자의 성능 저하를 방지할 수 있으며, 입출력 단자의 위치를 집중시킴에 따라 추가적인 인쇄선 또는 본딩 와이어의 연결에 따른 비용을 절감할 수 있다.
Abstract translation: 本发明涉及一种变压器。 根据本发明的一个实施例的使用对称印刷图案的变压器包括：板，印刷在板上彼此间隔一定距离的多个第一印刷线; 印刷在板上彼此间隔一定距离的多个第二印刷线; 将多个第一印刷线彼此连接的第一接合线; 以及将所述多个第二印刷线彼此连接的第二接合线，其中所述第一印刷线和所述第二印刷线分别在所述板上印刷为对称印刷图案，并且所述第一接合线和所述第二接合线分别对称 形成。 因此，可以防止连接到变压器的对称元件的性能劣化，并且可以通过集中输入和输出端子的位置来降低连接附加印刷线或接合线的成本。
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公开(公告)号：WO2014017699A1
公开(公告)日：2014-01-30
申请号：PCT/KR2012/008598
申请日：2012-10-19
Applicant: 숭실대학교산학협력단
CPC classification number: H03F3/211 , H03F1/0283 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/3022 , H03F3/3028 , H03F3/45179 , H03F3/45237 , H03F2200/405 , H03F2200/408 , H03F2200/516 , H03F2203/45481 , H03F2203/45544 , H03F2203/45594 , H03F2203/45631
Abstract: 본 발명은 스택 구조를 가지는 전력 증폭기에 관한 것으로, 본 발명의 일 실시예에 따른 스택 구조를 가지는 전력 증폭기는, 전원으로부터 전원전압이 인가되고, 입력 신호를 입력받아 증폭하는 제1 구동 증폭단과, 전원 입력단이 상기 제1 구동 증폭단의 접지단과 연결되어 가상 접지전압이 인가되고, 입력단이 상기 제1 구동 증폭단의 출력단과 연결되어 상기 제1 구동 증폭단의 출력 신호를 입력받아 증폭하는 제2 구동 증폭단과, 상기 전원으로부터 상기 전원전압이 인가되고, 입력단이 상기 제2 구동 증폭단의 출력단과 연결되어 상기 제2 구동 증폭단의 출력 신호를 입력받아 증폭하는 전력 증폭단을 포함한다. 이에 따라, 다단 증폭기를 구성하는 복수의 구동 증폭단을 스택 구조로 연결시킴으로써, 전원전압을 공급하는 레귤레이터의 개수를 줄이고, 집적 회로의 설계 면적을 줄일 수 있다.
Abstract translation: 本发明涉及具有堆叠结构的功率放大器。 具有根据本发明的一个实施例的堆叠结构的功率放大器包括：第一驱动放大器级，从电源施加电源电压并将输入信号作为输入，并将输入信号放大 ; 第二驱动放大器级，其具有连接到第一驱动放大器级的接地端的电源输入端，使得虚拟接地电压被施加到电力输入端，并且具有连接到第一驱动放大器级的输出端的输入端 使得第一驱动放大器级的输出信号被输入到输入端并被放大; 以及从电源施加电源电压的功率放大器级，并且其输入端连接到第二驱动放大器级的输出端，使得第二驱动放大器级的输出信号被输入到 输入端并放大。 根据本发明，构成多级放大器的多个驱动放大器级连接到堆叠结构中，从而减少提供电源电压的稳压器的数量，并减小用于设计集成电路的面积。
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Patent Agency Ranking
公开(公告)号：KR101196839B1
公开(公告)日：2012-11-01
申请号：KR1020110089617
申请日：2011-09-05
Applicant: 숭실대학교산학협력단
CPC classification number: H01F27/2804 , H01F27/40 , H01F2027/2814 , H05K1/165 , H05K3/222 , H05K2203/049
Abstract: PURPOSE: A transformer using a symmetrical printed pattern is provided to reduce costs due to the connection of a bonding wire or an additional print line by concentrating the position of input and output terminals. CONSTITUTION: A plurality of first print lines(210) is printed on a substrate(200). A plurality of second print lines(220) is printed on the substrate. A first bonding wire(230) connects the plurality of first print lines. A second bonding wire(240) connects the plurality of second print lines. The first print line and the second print line are respectively includes a coil print line and a connection print line.
Abstract translation: 目的：提供使用对称印刷图案的变压器，以通过集中输入和输出端子的位置来降低由于接合线或附加打印线的连接造成的成本。 构成：多个第一印刷线（210）印刷在基板（200）上。 多个第二印刷线（220）印刷在基板上。 第一接合线（230）连接多条第一印刷线。 第二接合线（240）连接多个第二印刷线。 第一印刷线和第二印刷线分别包括线圈印刷线和连接印刷线。
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公开(公告)号：KR101392888B1
公开(公告)日：2014-05-08
申请号：KR1020120131050
申请日：2012-11-19
Applicant: 숭실대학교산학협력단
IPC: H01L23/48
CPC classification number: H01L23/5384 , H01L23/481 , H01L23/50 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73257 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: The present invention relates to power supply apparatus for three dimensional (3D) semiconductor. According to the present invention, provided is the power supply apparatus for 3D semiconductor in which a plurality of first through silicon via (TSV) and second TSV are installed. A plurality of integrated circuits (IC) are mounted on PCB and connect the first TSV and second TSV. A first PCB line, formed on the PCB, providing a first voltage is connected to the bottom of the first TSV formed at the lowest IC among the ICs. A second PCB line, formed on the PCB, providing a second voltage is connected to the top of the second TSV formed at the highest IC. According to the power supply apparatus for 3D semiconductor, the operation performance of the whole system can be improved by reducing a difference in the performance of each IC and setting voltage difference identical between power voltage and connection voltage on each IC by differentiating an IC in which external connection power is supplied from an IC in which external power voltage is supplied.
Abstract translation: 本发明涉及用于三维（3D）半导体的电源装置。 根据本发明，提供了一种其中安装了多个第一至第二硅通孔（TSV）和第二TSV的用于3D半导体的电源装置。 多个集成电路（IC）安装在PCB上并连接第一TSV和第二TSV。 形成在PCB上的第一PCB线路，提供第一电压，连接到IC中最低IC上形成的第一TSV的底部。 在PCB上形成的提供第二电压的第二PCB线连接到在最高IC形成的第二TSV的顶部。 根据3D半导体电源装置，可以通过减少每个IC的性能差异来设定整个系统的操作性能，并且通过对IC中的电源电压和连接电压之间的电压差进行差分化， 从提供外部电源电压的IC提供外部连接电力。
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公开(公告)号：KR101350388B1
公开(公告)日：2014-01-15
申请号：KR1020120132977
申请日：2012-11-22
Applicant: 숭실대학교산학협력단
CPC classification number: H01L25/0657 , G05F3/16 , H01L2924/0002 , H01L2924/00
Abstract: The present invention relates to an integrated circuit having a stack structure. According to the present invention, provided is an integrated circuit having a stack structure, comprising: a first integrated circuit of which a power supply voltage is applied to a power input terminal; and a second integrated circuit of which a power input terminal is connected to a ground terminal of the first integrated circuit, of which voltage is applied to a central node formed by the connection, and of which a ground terminal is connected to a ground power supply voltage, wherein the power supply voltage is divided into first and second voltages to be each supplied to the first and second integrated circuits. The integrated circuit having a stack structure can connect the integrated circuits with the stack structure to reduce the number of pads and operate the integrated circuits at a high power supply voltage. In addition, the integrated circuit can reduce the number of pads to lower production costs and can operate the integrated circuits at a low power supply voltage even though a high power supply voltage is applied to reduce power consumption.
Abstract translation: 本发明涉及具有堆叠结构的集成电路。 根据本发明，提供一种具有堆叠结构的集成电路，包括：第一集成电路，其电源电压施加到电力输入端; 以及第二集成电路，其电源输入端子连接到所述第一集成电路的接地端子，所述第一集成电路的电压被施加到由所述连接形成的中心节点，并且其接地端子连接到地电源 电压，其中电源电压被分成要被提供给第一和第二集成电路的第一和第二电压。 具有堆叠结构的集成电路可以将集成电路与堆叠结构连接，以减少焊盘的数量并在高电源电压下操作集成电路。 此外，即使施加高电源电压以降低功耗，集成电路可以减少焊盘的数量以降低生产成本并且可以以低电源电压操作集成电路。
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公开(公告)号：KR101338015B1
公开(公告)日：2013-12-09
申请号：KR1020120082535
申请日：2012-07-27
Applicant: 숭실대학교산학협력단
CPC classification number: H03F3/211 , H03F1/0283 , H03F3/195 , H03F3/213 , H03F3/245 , H03F3/3022 , H03F3/3028 , H03F3/45179 , H03F3/45237 , H03F2200/405 , H03F2200/408 , H03F2200/516 , H03F2203/45481 , H03F2203/45544 , H03F2203/45594 , H03F2203/45631
Abstract: The present invention relates to a power amplifier which has a stack structure. The power amplifier includes: a first driving amplifier stage in which a power supply voltage is applied from a power source and which receives and amplifies an input signal; a second driving amplifier stage in which a virtual grounding voltage is applied by being connected to the grounding stage of the first driving amplifier stage at a power input stage and which receives and amplifies the output signal of the first driving amplifier stage by being connected to the output stage of the first driving amplifier stage at the input stage; and power amplifier stage in which the power supply voltage is applied from the power source and which receives and amplifies the output signal of the second driving amplifier stage by being connected to the output stage of the second driving amplifier stage at the input stage. According to the forementioned, the power amplifier is able to reduce the number of regulators which supply the power supply voltage and also reduce the designed area of an integrated circuit by connecting multiple driving amplifier stages which comprise a multi-stage amplifier in the stack structure. [Reference numerals] (AA) Input;(BB) Output
Abstract translation: 本发明涉及具有堆叠结构的功率放大器。 功率放大器包括：第一驱动放大器级，其中从电源施加电源电压并且其接收和放大输入信号; 第二驱动放大级，其中通过在功率输入级连接到第一驱动放大器级的接地级并且通过连接到第一驱动放大器级的输出信号来接收和放大第一驱动放大器级的输出信号来施加虚拟接地电压 在输入级的第一驱动放大器级的输出级; 以及功率放大级，其中从电源施加电源电压，并且通过在输入级连接到第二驱动放大器级的输出级来接收和放大第二驱动放大器级的输出信号。 根据前述，功率放大器能够减少提供电源电压的调节器的数量，并且还通过在堆叠结构中连接包括多级放大器的多个驱动放大器级来减小集成电路的设计面积。 （标号）（AA）输入;（BB）输出
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公开(公告)号：KR101326355B1
公开(公告)日：2013-11-11
申请号：KR1020120084824
申请日：2012-08-02
Applicant: 숭실대학교산학협력단
Abstract: The present invention relates to a method for manufacturing an integrated circuit for wireless communication and an integrated circuit thereof. According to the present invention, the method for manufacturing the integrated circuit for wireless communication and the integrated circuit thereof includes a step for forming an inductor on the surface of the substrate, a step for forming an insulating layer on the upper surface of the substrate to cover the upper surface of the inductor, a step for exposing the input and the output terminal of the inductor by forming a via hole in a part of the insulating layer, a step for forming a metal layer for integrating a passive device on the upper surface of the insulating layer, filling the via hole with a conductive material, and connecting the input and the output terminal to the metal layer, a step for forming a protection layer on the upper surface of the insulating layer to cover the metal layer, and a step for removing a part of the lower part of the insulating layer and a part of the substrate to expose the inductor from the lower part of the substrate. According to the method for manufacturing the integrated circuit for wireless communication and the integrated circuit thereof, a part of the substrate corresponding to the inductor part in the integrated circuit is removed to remove an eddy current generated in the substrate and prevent power loss. Therefore, the communication efficiency of wireless communication between the integrated circuit and the transmission efficiency of power are improved.
Abstract translation: 本发明涉及无线通信用集成电路的制造方法及其集成电路。 根据本发明，用于无线通信的集成电路的制造方法及其集成电路包括在基板的表面上形成电感器的步骤，在基板的上表面上形成绝缘层的步骤， 覆盖电感器的上表面，通过在绝缘层的一部分中形成通孔来暴露电感器的输入端子和输出端子的步骤，用于形成用于将无源器件集成在上表面上的金属层的步骤 的绝缘层，用导电材料填充所述通孔，并且将所述输入端和所述输出端连接到所述金属层;在所述绝缘层的上表面上形成保护层以覆盖所述金属层的步骤，以及 用于去除绝缘层的下部的一部分和基板的一部分以从基板的下部露出电感器的步骤。 根据制造无线通信用集成电路的方法及其集成电路，去除与集成电路中的电感器部分对应的部分基板，以去除在基板中产生的涡流并防止功率损耗。 因此，提高了集成电路之间的无线通信的通信效率和功率的传输效率。
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