公开(公告)号：US20230291421A1

公开(公告)日：2023-09-14

申请号：US17690867

申请日：2022-03-09

Applicant: Apple Inc.

Inventor： Hongrui Wang ,  Abbas Komijani ,  Xinhua Chen

IPC: G05F1/46 ,  H04B1/04

CPC classification number: G05F1/468 ,  G05F1/461 ,  H04B1/04 ,  H04B2001/0408

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

公开(公告)号：US20230093529A1

公开(公告)日：2023-03-23

申请号：US17941767

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Hongrui Wang ,  Abbas Komijani

IPC: H03B5/12 ,  H03L7/093 ,  H03L7/089

Abstract: Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.

公开(公告)号：US20230092708A1

公开(公告)日：2023-03-23

申请号：US17942807

申请日：2022-09-12

Applicant: Apple Inc.

Inventor： Reetika Kumari Agarwal ,  Abbas Komijani

IPC: G05F1/575 ,  G05F1/59

Abstract: Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.

公开(公告)号：US11296802B1

公开(公告)日：2022-04-05

申请号：US17031753

申请日：2020-09-24

Applicant: Apple Inc.

Inventor： Hongrui Wang ,  Abbas Komijani ,  Saihua Lin ,  Sohrab Emami-Neyestanak

IPC: H04B17/21 ,  H04B17/345 ,  H03B5/18

Abstract: An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

公开(公告)号：US20220094451A1

公开(公告)日：2022-03-24

申请号：US17031753

申请日：2020-09-24

Applicant: Apple Inc.

Inventor： Hongrui Wang ,  Abbas Komijani ,  Saihua Lin ,  Sohrab Emami-Neyestanak

IPC: H04B17/21 ,  H03B5/18 ,  H04B17/345

Abstract: An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

公开(公告)号：US11165389B1

公开(公告)日：2021-11-02

申请号：US17131168

申请日：2020-12-22

Applicant: Apple Inc.

Inventor： Abbas Komijani ,  Hongrui Wang ,  Sohrab Emami-Neyestanak

IPC: H03B5/12

Abstract: An electronic device may include a transceiver with mixer circuitry that up-converts or down-converts signals based on a voltage-controlled oscillator (VCO) signal. The transceiver circuitry may include first, second, third, and fourth VCOs. Each VCO may include a VCO core that receives a control voltage and an inductor coupled to the VCO core. Fixed linear capacitors may be coupled between the VCO cores. A switching network may be coupled between the VCOs. Control circuitry may place the VCO circuitry in one of four different operating modes and may switch between the operating modes to selectively control current direction in each of the inductors. The VCO circuitry may generate the VCO signal within a respective frequency range in each of the operating modes. The VCO circuitry may exhibit a relatively wide frequency range across all of the operating modes while introducing minimal phase noise to the system.