公开(公告)号：WO1998029839A1

公开(公告)日：1998-07-09

申请号：PCT/US1997024088

申请日：1997-12-30

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  VASWANI, Gautam, P. ,  LARSON, Michael ,  DYE, Tom

IPC: G06T15/10

CPC classification number: G06T15/04

Abstract: In a computer system having a host processor, a peripheral graphics device, a display screen, and a memory, a non-homogenous second order perspective texture mapping process. Polygon coordinates, am,n, defining a texture polygon, are received. Initial values are received for a set of parameters including umain, vmain, dvortho, dvmain, duortho, dumain, d uortho, d umain, d vortho, d vmain, duortho-ADD, and dvortho-ADD. The texture polygon includes span regions. A span value, j, is set to an initial value to designate an initial span region of the texture polygon in (m, n) polygon coordinate space. The total number of rows, nmax, is determined for the current span region of the polygon. The total number of polygon coordinates, mmax, in the current row, n, of the texture polygon is determined. An (x, y) display coordinate, corresponding to the current polygon coordinate, am,n, is set by translating from (m, n) polygon space to (x, y) display coordinate space. Texture coordinates, u(am,n) and v(am,n), are determined, according to the present invention, for each polygon coordinate, am,n, using linear interpolation based on a set of relationships that utilize the above parameters without using a repetitive divide operation. A display pixel of a color determined according to texture coordinates, u(am,n) and v(am,n), is rendered on a display screen at the determined (x, y) position.

Abstract translation: 在具有主机处理器，外围图形设备，显示屏幕和存储器的计算机系统中，非均匀的二阶透视纹理映射处理。 接收定义纹理多边形的多边形坐标，am，n。 对于一组参数，包括umain，vmain，dvortho，dvmain，duortho，dumain，d 2 uortho，d 2，v 2，v 2，v 2，v 2，v 2，d 2， 和dvortho-ADD。 纹理多边形包括跨度区域。 跨度值j被设置为初始值以指定（m，n）多边形坐标空间中的纹理多边形的初始跨度区域。 为多边形的当前跨度区域确定总行数nmax。 确定纹理多边形的当前行n中的多边形坐标的总数，mmax。 通过从（m，n）多边形空间转换为（x，y）显示坐标空间来设置与当前多边形坐标am，n对应的（x，y）显示坐标。 根据本发明，根据本发明确定纹理坐标u（am，n）和v（am，n），对于每个多边形坐标am，n，使用基于利用上述参数的一组关系的线性插值而没有 使用重复划分操作。 根据纹理坐标u（am，n）和v（am，n）确定的颜色的显示像素在确定的（x，y）位置的显示屏幕上呈现。

公开(公告)号：WO1998029837A1

公开(公告)日：1998-07-09

申请号：PCT/US1997023528

申请日：1997-12-23

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  EINKAUF, Mark, A. ,  LARSON, Michael, K.

IPC: G06T15/10

CPC classification number: G06T15/04

Abstract: A method for computing input parameters used in a non-homogeneous second order perspective texture mapping process using interpolation. The present invention receives a polygon primitive (e.g., triangle) including screen display coordinates and texture map coordinates for each vertex (vmin, vmid, and vmax). Based on vertex information including perspective weight, w, screen display coordinates and texture map coordinates are determined for midpoint (i and j) of the two triangle slopes opposite the triangle's major slope. Based on a determined quadratic equation of the triangle's major slope, screen coordinates and texture map coordinates are determined at several selected points (e.g., imain, jmain, and midmain) along the major slope that corresponds to the i, j, and vmid points. From these values, quadratic coefficients a1, a2, and du_ortho_add are computed and also quadratic coefficients b1, b2 and dv_ortho_add are computed. The above values, parameters u_main, du_main (change in u over change in y), d2u_main (changed in DELTA u over change in DELTA y), du_ortho (change in u over change in x), d2u_ortho (change in DELTA u over change in DELTA x), v_main, dv_main (change in v over change in y), d2v_main (change in DELTA v over change in DELTA y), dv_ortho (change in v over change in x), and d2v_ortho (change in DELTA v over change in DELTA x) are computed and forwarded to a non-homogenous second order perspective texture mapping process using interpolation. The above texture mapping process is extremely efficient as it is free of division operations during the interpolation.

Abstract translation: 一种用于计算在使用插值的非均匀二阶透视纹理映射处理中使用的输入参数的方法。 本发明接收包括每个顶点（vmin，vmid和vmax）的屏幕显示坐标和纹理映射坐标的多边形原语（例如，三角形）。 基于包括透视权重的顶点信息，w，与三角形主要斜率相反的两个三角形斜率的中点（i和j）确定屏幕显示坐标和纹理贴图坐标。 基于三角形主坡的确定的二次方程，沿着对应于i，j和vmid点的主斜率的几个选定点（例如，imain，jmain和midmain）确定屏幕坐标和纹理图坐标。 从这些值中，计算二次系数a1，a2和du_ortho_add，并且还计算二次系数b1，b2和dv_ortho_add。 以上值，参数u_main，du_main（在u中更改为u），d2u_main（在DELTA中更改为DELTA y中的更改），du_ortho（x更改为x中的更改），d2u_ortho（更改为DELTA u） 在DELTA x）中，v_main，dv_main（在v中更改y中的更改），d2v_main（DELTA v中的更改在DELTA y中的更改），dv_ortho（x中更改x中的更改）和d2v_ortho（DELTA v中的更改 计算DELTA x中的变化，并使用插值将其转发到非均匀的二阶透视纹理映射过程。 上述纹理映射处理是非常有效的，因为它在插值期间没有分割操作。

公开(公告)号：WO1998029807A1

公开(公告)日：1998-07-09

申请号：PCT/US1997023907

申请日：1997-12-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  TARQUINI, Richard

IPC: G06F09/46

CPC classification number: G06F9/4881 ,  G06F9/45537 ,  G06F13/102

Abstract: The problems associated with CPU hoggin when running legacy applications, such as DOS applications, on a modern operating system, such as Windows 95, are overcome by creating a Virtual Device Driver VxD to manage needs for guaranteed CPU access by various processes and devices. The virtual device driver utilizes services of Virtual Machine Manager to guarantee CPU access by requesting processes and devices.

Abstract translation: 在现代操作系统（如Windows 95）上运行旧版应用程序（如DOS应用程序）时，与CPU hoggin相关的问题可以通过创建虚拟设备驱动程序VxD来管理各种进程和设备的保证CPU访问的需求。 虚拟设备驱动程序利用虚拟机管理器的服务来通过请求进程和设备来保证CPU访问。

公开(公告)号：WO1998023029A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021213

申请日：1997-11-17

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  PASTORELLO, Douglas

IPC: H03H17/02

CPC classification number: H03H17/06 ,  H03H17/0226

Abstract: A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.

Abstract translation: 降低功率FIR滤波器可以用作Δ西格玛ADC的数字抽取滤波器。 FIR滤波器利用串行比特流，该比特流是滤波器的控制路径的一部分。 因此，可以根据呈现在Δ-Σ调制器的输出处的数据来控制包括滤波器的电路的操作。 特别地，可以仅针对给定的数字状态（例如，数字1状态）使能滤波器操作。 因此，滤波器操作可以仅来自串行比特流的典型的一半比特，并且数字滤波器的功率使用量显着降低。

公开(公告)号：WO1998014905A2

公开(公告)日：1998-04-09

申请号：PCT/US1997017396

申请日：1997-09-26

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  VASWANI, Gautam

IPC: G06T00/00

CPC classification number: G06T15/10

Abstract: A graphics subsystem includes hardware and/or software for permitting mip-maps to be dynamically switched based upon depth (Z) values. In addition, the system generates a SHIFT signal to permit automatic adjustment of texture parameters to facilitate retrieval of texture maps. The system includes a mip-map select logic or routine that compares the depth value of a pixel to be rendered with predetermined depth values. The depth values may be stored in a plurality of depth registers, and compared with the depth value of a pixel in a plurality of associated comparators. A mip-map is selected based upon the comparisons, and the SHIFT signal is generated to indicate the order of change with respect to a base reference mip-map. A texture engine receives the SHIFT signal and uses the associated base address of the selected mip-map and shifted texture parameters to define an address for the texture map.

Abstract translation: 图形子系统包括用于基于深度（Z）值来允许mip-map被动态切换的硬件和/或软件。 此外，系统产生SHIFT信号以允许纹理参数的自动调整以便于纹理贴图的检索。 该系统包括将要渲染的像素的深度值与预定深度值进行比较的mip-map选择逻辑或例程。 深度值可以存储在多个深度寄存器中，并且与多个相关比较器中的像素的深度值进行比较。 基于比较选择mip-map，并且生成SHIFT信号以指示相对于基本参考mip-map的改变顺序。 纹理引擎接收SHIFT信号，并使用所选择的mip-map和移位的纹理参数的相关联的基地址来定义纹理映射的地址。

公开(公告)号：WO1998014878A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017138

申请日：1997-09-22

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  DEVIC, Goran

IPC: G06F12/10

CPC classification number: G06F12/1081

Abstract: In a computer system, a peripheral graphics device (PGD) accesses a graphics buffer (GB) wherein the GB physical pages can be contiguous or discontiguous. A request is received to allocate memory for a GB of a predetermined size and handle. The number of pages within the size parameter is determined based on the page size used by the computer system and the buffer size needed. A first memory block is allocated for storing the GB and locked to prevent swapping. A starting virtual address of a CPU page table (CPU/PT) is accessed and mapped to a starting logical address to allow traversal of the CPU/PT by a user application. A second memory block is allocated for building a graphics device page table (GDPT) that can be accessed by a PGD. The logical address of each GB page is sequentially accessed and the corresponding physical address of each GB page is determined from the CPU/PT. The logical and physical addresses of each GB page are stored into the GDPT. If all physical pages of the GB are contiguous, the logical and physical addresses of the GB are stored into a database indexed by a user handle. Otherwise, the starting address of the GDPT is stored into the database indexed by a user handle. Provided that all of the GB physical pages are contiguous, the PGD accesses the GB by its starting physical address. Otherwise, the PGD uses the GDPT to access the discontiguous physical pages of the GB.

Abstract translation: 在计算机系统中，外围图形设备（PGD）访问图形缓冲器（GB），其中GB物理页面可以是连续的或不连续的。 接收到一个请求，以分配一个预定大小和句柄的GB的内存。 根据计算机系统使用的页面大小和所需的缓冲区大小来确定大小参数内的页数。 分配第一个存储块用于存储GB并锁定以防止交换。 CPU页面表（CPU / PT）的起始虚拟地址被访问并映射到起始逻辑地址，以允许用户应用程序遍历CPU / PT。 分配第二存储器块用于构建可由PGD访问的图形设备页表（GDPT）。 顺序访问每个GB页面的逻辑地址，并从CPU / PT确定每个GB页面的对应物理地址。 每个GB页面的逻辑地址和物理地址都存储在GDPT中。 如果GB的所有物理页面都是连续的，则将GB的逻辑地址和物理地址存储到由用户句柄索引的数据库中。 否则，GDPT的起始地址存储在由用户句柄索引的数据库中。 如果所有GB物理页面都是连续的，则PGD通过其起始物理地址访问GB。 否则，PGD使用GDPT来访问GB的不连贯的物理页面。

公开(公告)号：WO1998014865A2

公开(公告)日：1998-04-09

申请号：PCT/US1997017418

申请日：1997-09-26

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  DEVIC, Goran

IPC: G06F09/00

CPC classification number: G06F11/1004

Abstract: In a computer controlled graphics system, processes are provided for detecting errors incurred in a display list having variable length instruction/parameter (I/P) sets, the errors occurring during parameterization, transmission, branching, and storage of the display list. Each process includes generating a display list including I/P sets, each I/P set including n parameter words following an instruction word. In each embodiment, a display list is encoded, transmitted, stored in a memory unit, and verified. In one embodiment, the display list is encoded by storing into each instruction word of each I/P set a parity bit of a value representative of the parity of the whole I/P set. In another embodiment, the display list is encoded by storing within each instruction word of each I/P set an m-bit checksum value. The m-bit checksum value is generated by partitioning each I/P set into y m-bit partitions which are summed, ignoring overflow. In a third embodiment, a display list is encoded by appending each I/P set with a checksum word generated by summing the instruction word and each of the n parameter words of each I/P set, ignoring overflows. In each embodiment, the encoded display list is stored in a memory unit and later accessed for verification. In each embodiment, verification is performed by re-performing the respective encoding scheme for each I/P set. Upon detection of an error, corrective action, including a debug message can be taken.

Abstract translation: 在计算机控制的图形系统中，提供了用于检测具有可变长度指令/参数（I / P）集合的显示列表中发生的错误，显示列表的参数化，传输，分支和存储期间发生的错误的处理。 每个处理包括生成包括I / P集合的显示列表，每个I / P集合包括在指令字之后的n个参数字。 在每个实施例中，将显示列表编码，发送，存储在存储器单元中并进行验证。 在一个实施例中，显示列表通过将每个I / P集合的每个指令字存储在表示整个I / P集合的奇偶校验的值的奇偶校验位来编码。 在另一个实施例中，显示列表通过在每个I / P集合的每个指令字中存储m位校验和值进行编码。 通过将每个I / P集合划分为y个m位分区来生成m位校验和值，它们相加，忽略溢出。 在第三实施例中，通过将每个I / P集合与通过对指令字和每个I / P集合的n个参数字中的每一个进行求和而产生的校验和字进行编码，忽略溢出。 在每个实施例中，编码的显示列表存储在存储器单元中，并且稍后被访问以进行验证。 在每个实施例中，通过针对每个I / P集重新执行相应的编码方案来执行验证。 检测到错误后，可以采取包括调试消息在内的纠正措施。

公开(公告)号：WO1998011530A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016139

申请日：1997-09-10

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  JENKINS, Michael, V. ,  DONG, Quijie ,  VEESER, Edward, M.

IPC: G10H01/00

CPC classification number: G10H1/0091 ,  G10H2210/201 ,  G10H2210/281 ,  G10H2240/056 ,  G10H2250/121 ,  G10H2250/611 ,  G10K15/12

Abstract: A sound or music synthesizer includes a reverberation simulator having a substantially reduced volatile storage, random access memory, or buffer size in comparison to conventional reverberation simulators by decimating the sound signal prior to applying the sound signal to a reverberator and then interpolating the sound signal generated by the reverberator to restore the sample frequency. The substantial reduction in buffer size enables the usage of the reverberator in low-cost, reduced size and single-chip environments.

Abstract translation: 声音或音乐合成器包括与常规混响模拟器相比具有显着降低的易失性存储器，随机存取存储器或缓冲器大小的混响仿真器，通过在将声音信号施加到混响器之前抽取声音信号，然后内插产生的声音信号 由混响器恢复采样频率。 缓冲区大小的大幅降低使得混响器的使用成本低廉，体积小，单芯片环境。

公开(公告)号：WO1997008676A1

公开(公告)日：1997-03-06

申请号：PCT/US1996014062

申请日：1996-08-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  SHARMA, Sudhir

IPC: G09G01/16

CPC classification number: G09G5/393 ,  G09G5/36 ,  G09G2310/04

Abstract: A method is provided for refreshing data stored in a frame buffer. Data stored in the first area of the frame buffer are automatically refreshed during retrieval of such data for display generation. Data stored in a second area of a frame buffer is refreshed according to the following substeps. A determination is made as to whether selected data in the second area of the frame buffer is required during the generation of an upcoming display line. The selected data is read from the second area when such data from the second area of the frame buffer is required for generation of the upcoming display line. A refresh is initiated of at least a portion of the second area when data from the second area is not required for the generation of the upcoming display line and a time for refresh of the second area has been reached.

Abstract translation: 提供一种用于刷新存储在帧缓冲器中的数据的方法。 存储在帧缓冲器的第一区域中的数据在用于显示生成的这些数据的检索期间被自动刷新。 存储在帧缓冲器的第二区域中的数据根据​​以下子步骤进行刷新。 确定在即将到来的显示行的生成期间是否需要在帧缓冲器的第二区域中选择的数据。 当需要来自帧缓冲器的第二区域的数据来产生即将到来的显示行时，从第二区域读取所选择的数据。 当来自第二区域的数据不需要用于生成即将到来的显示行并且已经达到刷新第二区域的时间时，对第二区域的至少一部分进行刷新。

公开(公告)号：WO1996038913A1

公开(公告)日：1996-12-05

申请号：PCT/US1996008126

申请日：1996-05-31

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZHANG, Zhongxuan ,  DU, He

IPC: H03K05/13

CPC classification number: H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03K5/131 ,  H03K5/133 ,  H03L7/0891 ,  H03L7/0995

Abstract: A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, and a plurality of transistors for providing control voltages to the plurality of voltage controlled inverting delay cells. Preferably, each transistor has a drain connected to a reference voltage, and a source connected to a voltage controlled inverting delay cell paired to that transistor. Consequently, each transistor acts as a source-follower so that it provides a control voltage to its corresponding voltage controlled inverting delay cell which follows a control voltage driving its gate, thereby isolating the control voltage provided to its corresponding voltage controlled inverting delay cell from power supply noise.

Abstract translation: VCO包括通过将多个电压控制的反相延迟单元连接在一起形成的环形振荡器和用于向多个电压控制的反相延迟单元提供控制电压的多个晶体管。 优选地，每个晶体管具有连接到参考电压的漏极，以及连接到与该晶体管成对的电压控制反相延迟单元的源极。 因此，每个晶体管起到源极跟随器的作用，从而为其对应的受电压控制的反相延迟单元提供控制电压，该反相延迟单元遵循驱动其栅极的控制电压，从而将提供给其相应的电压控制反相延迟单元的控制电压与功率隔离 供应噪音。