公开(公告)号：US11908898B2

公开(公告)日：2024-02-20

申请号：US17456943

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

公开(公告)号：US11785860B2

公开(公告)日：2023-10-10

申请号：US16846497

申请日：2020-04-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Haiting Wang ,  Yanping Shen

IPC: H10N50/80 ,  H10B51/30 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B51/30 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/231 ,  H10N70/841

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

公开(公告)号：US20230261088A1

公开(公告)日：2023-08-17

申请号：US17669584

申请日：2022-02-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Hong Yu ,  Jianwei Peng ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/285

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/42392 ,  H01L29/78696

Abstract: Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

公开(公告)号：US11710771B2

公开(公告)日：2023-07-25

申请号：US17524043

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Judson R. Holt ,  Haiting Wang ,  Jagar Singh ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/6656 ,  H01L29/66242 ,  H01L29/66553 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

公开(公告)号：US11705508B2

公开(公告)日：2023-07-18

申请号：US17398479

申请日：2021-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/7851

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US11646361B2

公开(公告)日：2023-05-09

申请号：US17191886

申请日：2021-03-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/7851

Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.

公开(公告)号：US20230071998A1

公开(公告)日：2023-03-09

申请号：US17551346

申请日：2021-12-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

公开(公告)号：US20230065924A1

公开(公告)日：2023-03-02

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11563085B2

公开(公告)日：2023-01-24

申请号：US17243832

申请日：2021-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US11545574B2

公开(公告)日：2023-01-03

申请号：US16994915

申请日：2020-08-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Rinus Lee ,  Sipeng Gu ,  Yue Hu

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Structures for a single diffusion break and methods of forming a structure for a single diffusion break. A cut is formed in a semiconductor fin. A single diffusion break includes a first dielectric layer in the cut and a second dielectric layer over the first dielectric layer. The first dielectric layer is comprised of a first material, and the second dielectric layer is comprised of a second material having a different composition than the first material. The second dielectric layer includes a first portion over the first dielectric layer and a second portion over the first portion. The first portion of the second dielectric layer has a first horizontal dimension, and the second portion of the second dielectric layer has a second horizontal dimension that is greater than the first horizontal dimension.