公开(公告)号：DE3382278D1

公开(公告)日：1991-06-13

申请号：DE3382278

申请日：1983-11-08

Applicant: IBM

Inventor： PATEL ARVIND MOTIBHAI

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15

Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).

公开(公告)号：AU593096B2

公开(公告)日：1990-02-01

申请号：AU7188887

申请日：1987-04-23

Applicant: IBM

Inventor： EGGENBERGER JOHN SCOTT ,  PATEL ARVIND MOTIBHAI

IPC: H03M1/22 ,  H03M5/14 ,  H03M7/14 ,  H03M7/46

Abstract: Methods and apparatus for implementing PRML codes are disclosed. Specifically considered in detail are rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/6) are provided for any partial response (PR) signalling system employing maximum likelihood (ML) detection.

公开(公告)号：ZA837726B

公开(公告)日：1984-08-29

申请号：ZA837726

申请日：1983-10-17

Applicant: IBM

Inventor： PATEL ARVIND MOTIBHAI

IPC: G06F11/10 ,  G06F20060101 ,  G06F11/08 ,  G06K20060101 ,  G11B5/09 ,  H03M13/00 ,  H03M13/15 ,  G06F ,  G06K

公开(公告)号：DK108384A

公开(公告)日：1984-08-29

申请号：DK108384

申请日：1984-02-27

Applicant: IBM

Inventor： PATEL ARVIND MOTIBHAI

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  G06F

Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).

公开(公告)号：CH630196A5

公开(公告)日：1982-05-28

申请号：CH327078

申请日：1978-03-28

Applicant: IBM

Inventor： EIGE JOHN JACOB ,  PATEL ARVIND MOTIBHAI ,  ROBERTS SPENCER DONALD ,  STEDMAN DAVID

IPC: G11B15/43 ,  B65H23/18 ,  G11B15/46 ,  G11B15/48 ,  G11B15/54 ,  G11B27/13

公开(公告)号：DE2853892A1

公开(公告)日：1979-06-28

申请号：DE2853892

申请日：1978-12-14

Applicant: IBM

Inventor： PATEL ARVIND MOTIBHAI

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G11B5/09

Abstract: Where data is recorded on logically independent sets of parallel channels or tracks, the correction of error of very long (infinite) length cannot be advantageously treated by conventional coding methods unlike finite length error such as single shot or burst noise. To ensure the correction of channels in error from data recovered from a multi-channel storage medium, a fixed number of channels per set are dedicated to error checking bits. In this invention, more than the usual number of channels in error in any one set are made correctable by adaptively reallocating the unused redundant channels in the other set. This is accomplished by encoding and recording in the first redundant channel in each set vertical parity checks limited to that set while encoding and recording in the second redundant channel of each set, the parity of data taken over both sets of channels in a predetermined positively or negatively sloped direction. With this type of parity information so recorded, then the data obtained from up to three known erroneous channels in any one set may be corrected, provided that two sets together aggregate not more than four channels in error. Advantageously, the vertical and cross-parity checking information can also be used to generate an internal channel-in-error pointer for the first erroneous track in each set. Additionally, this data can be made to yield a second internal channel-in-error pointer in at least one of the sets. Lastly, error patterns are identified upon decoding at the intersection of at least two error syndromes one of which is derived from cross-parity checking bits.

公开(公告)号：DE2262070A1

公开(公告)日：1973-07-05

申请号：DE2262070

申请日：1972-12-19

Applicant: IBM

Inventor： HONG SE JUNE ,  PATEL ARVIND MOTIBHAI

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/13 ,  H03M13/19

Abstract: 1371970 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 21 Nov 1972 [20 Dec 1971] 53670/72 Heading G4A Data is operated on according to a matrix H (defined in the Specification) by pairs of shift registers, each pair of registers operating on a sub-matrix defining a partition of matrix H, and further registers to produce check bits for use in error correction after utilization of the data, e.g. in a tape unit or transmission channel. In a specific example, 2-bit bytes B 0 -B 30 corresponding to the first partition of matrix H are supplied serially to the first pair of shift registers SRB1, SRB2, the former performing modulo 2 addition of corresponding bits in successive bytes, while the latter performs modulo 2 addition of the incoming byte to the product of the register contents with the companion matrix corresponding to the primitive polynomial 1+ x 2 + x 5 used to generate the sub-matrix of the first partition of matrix H. A similar pair of shift registers is used for bytes A 0 -A 6 corresponding to a second partition of matrix H generated by the primitive polynomial 1 + x + x 3 . Outputs 11-17 and 21-25 of the registers are modulo 2 added as shown to form check bytes C1-C3. The same arrangement may be used to generate error syndromes S1-S3 after utilization of the data, the check bits associated with the data being included in the modulo 2 addition as shown. An error byte in the first or second partition results in at least two non-zero syndrome bytes, the first being respectively S1 and S2, and an error in a check byte results in a single non-zero syndrome byte corresponding to the check byte in error. The actual erroneous byte in the partition identified by the syndrome can be determined by entering the first non-zero byte into the appropriate shift register SRB2, SRA2 and shifting until the contents match the remaining non-zero syndrome bytes, the number of shifts then indicating the byte position within the partition. Correction of the erroneous byte is performed by exclusive OR of the appropriate syndrome byte error pattern with the byte, Fig. 6 (not shown).