公开(公告)号：FR2325105A1

公开(公告)日：1977-04-15

申请号：FR7413430

申请日：1974-04-10

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HONG SE JUNE ,  HSIAO MU-YUE ,  PATEL ARVIND M

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.

公开(公告)号：DE2262070A1

公开(公告)日：1973-07-05

申请号：DE2262070

申请日：1972-12-19

Applicant: IBM

Inventor： HONG SE JUNE ,  PATEL ARVIND MOTIBHAI

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/13 ,  H03M13/19

Abstract: 1371970 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 21 Nov 1972 [20 Dec 1971] 53670/72 Heading G4A Data is operated on according to a matrix H (defined in the Specification) by pairs of shift registers, each pair of registers operating on a sub-matrix defining a partition of matrix H, and further registers to produce check bits for use in error correction after utilization of the data, e.g. in a tape unit or transmission channel. In a specific example, 2-bit bytes B 0 -B 30 corresponding to the first partition of matrix H are supplied serially to the first pair of shift registers SRB1, SRB2, the former performing modulo 2 addition of corresponding bits in successive bytes, while the latter performs modulo 2 addition of the incoming byte to the product of the register contents with the companion matrix corresponding to the primitive polynomial 1+ x 2 + x 5 used to generate the sub-matrix of the first partition of matrix H. A similar pair of shift registers is used for bytes A 0 -A 6 corresponding to a second partition of matrix H generated by the primitive polynomial 1 + x + x 3 . Outputs 11-17 and 21-25 of the registers are modulo 2 added as shown to form check bytes C1-C3. The same arrangement may be used to generate error syndromes S1-S3 after utilization of the data, the check bits associated with the data being included in the modulo 2 addition as shown. An error byte in the first or second partition results in at least two non-zero syndrome bytes, the first being respectively S1 and S2, and an error in a check byte results in a single non-zero syndrome byte corresponding to the check byte in error. The actual erroneous byte in the partition identified by the syndrome can be determined by entering the first non-zero byte into the appropriate shift register SRB2, SRA2 and shifting until the contents match the remaining non-zero syndrome bytes, the number of shifts then indicating the byte position within the partition. Correction of the erroneous byte is performed by exclusive OR of the appropriate syndrome byte error pattern with the byte, Fig. 6 (not shown).

公开(公告)号：DE2961000D1

公开(公告)日：1981-12-24

申请号：DE2961000

申请日：1979-07-25

Applicant: IBM

Inventor： HONG SE JUNE

IPC: G01R31/28 ,  G01R31/02 ,  G01R31/04 ,  G01R31/3185

Abstract: This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros. In the preferred embodiment a more complex but still relatively simple bit pattern can test all the interconnection nets to determine if there are shorts between any of the nets.

公开(公告)号：DE2260846A1

公开(公告)日：1973-06-20

申请号：DE2260846

申请日：1972-12-13

Applicant: IBM

Inventor： HONG SE JUNE ,  PATEL ARVIND MOTIBHAI

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19

Abstract: 1372907 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 21 Nov 1972 [15 Dec 1971] 53673/72 Heading G4A A plurality of check bytes are added to a sequence of message bytes according to a matrix H which includes submatrices each of which operates on distinct portions of the message bytes, and after utilization, the message and check bytes are operated on to form a plurality of syndrome bytes which are then decoded to produce error pointers which indicate the bits in error within a single byte when all other bytes are error free. For example, a message comprising two partitions having 31 and 7 two-bit bytes respectively is encoded with three check bytes of 2, 2 and 3 bits. Syndrome bytes of 2, 2 and 3 bits are generated, each byte being separately decoded and the decoded outputs being gated together in appropriate combinations to indicate which bits are in error, there being a gating circuit for each information byte and, optionally, for each check byte. The check bytes may be encoded by exclusive OR circuits each of which operates on message bits corresponding to the 1's in one row of the appropriate submatrix. The syndrome bytes are generated in a similar manner, each exclusive OR circuit receiving the appropriate check bit as an additional input. The syndrome bytes are decoded by respective gate circuits to produce a separate output for each possible combination of syndrome bits in the byte, and for each message bit, groups of outputs of the syndrome decoders, selected according to the matrix H, are gated together to produce an error pointer for each message bit. Each error pointer is exclusive OR-ed with the corresponding message bit to effect correction.

公开(公告)号：DE3381062D1

公开(公告)日：1990-02-08

申请号：DE3381062

申请日：1983-10-05

Applicant: IBM

Inventor： HONG SE JUNE ,  NAIR RAVINDRA

IPC: G06F7/24 ,  G06F7/02 ,  G06F7/22

公开(公告)号：DE2428040A1

公开(公告)日：1975-01-09

申请号：DE2428040

申请日：1974-06-11

Applicant: IBM

Inventor： HONG SE JUNE ,  OSTAPKO DANIEL LAWRENCE

IPC: H03M7/40 ,  G11B20/14 ,  H04L25/48 ,  H04L25/49 ,  H03K13/00

Abstract: The encoding circuits of this invention provide signals for representing binary data in a storage medium or in a transmission system as a waveform that has a small constrained value of accumulated difference between its positive and negative portions. The waveform has minimum and maximum run lengths between transitions between positive and negative values so that it provides both high density and good clocking. Several new codes are described which can be implemented with fewer logic and storage components than prior codes of this general type.

公开(公告)号：DE3279427D1

公开(公告)日：1989-03-09

申请号：DE3279427

申请日：1982-05-06

Applicant: IBM

Inventor： HONG SE JUNE ,  NAIR RAVINDRA KUMAR ,  SHAPIRO EUGENE

IPC: G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  G06F15/60

Abstract: The apparatus determines the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with a number of identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbour processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells. The arrangement gives reduced design times.

公开(公告)号：DE2425823A1

公开(公告)日：1975-01-02

申请号：DE2425823

申请日：1974-05-28

Applicant: IBM

Inventor： BOSSEN DOUGLAS CRAIG ,  HONG SE JUNE ,  HSIAO MU-YUE ,  PATEL ARVIND MOTIBHAI

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19 ,  H03K13/32

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.

公开(公告)号：DE3485201D1

公开(公告)日：1991-11-28

申请号：DE3485201

申请日：1984-06-28

Applicant: IBM

Inventor： BURSTEIN MICHAEL ,  HONG SE JUNE ,  PELAVIN RICHARD NEIL

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H01L23/52

Abstract: For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas (G-, G + ) of decreasing size, the set of components is partitioned into subsets (X', X") which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.

公开(公告)号：DE2357004A1

公开(公告)日：1974-05-30

申请号：DE2357004

申请日：1973-11-15

Applicant: IBM

Inventor： HONG SE JUNE ,  PATEL ARVIND MOTIBHAI

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00