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    DATA RETURNED RESPONSIVE TO EXECUTING A START SUBCHANNEL INSTRUCTION
    63.
    发明专利
    DATA RETURNED RESPONSIVE TO EXECUTING A START SUBCHANNEL INSTRUCTION 未知

    公开(公告)号：CA2819161A1

    公开(公告)日：2012-12-13

    申请号：CA2819161

    申请日：2012-05-25

    Applicant: IBM

    Inventor： SZWED PETER KENNETH ,  OAKES KENNETH JAMES ,  SUTTON PETER GRIMM ,  DRIEVER PETER DANA ,  YUDENFRIEND HARRY ,  GLASSEN STEVEN GARDNER

    IPC: G06F13/12 ,  G06F13/28

    Abstract: Provided is a method of executing a Start Subchannel instruction in a computing environment comprising main storage and storage class memory, said method comprising: responsive to determining that a subchannel identified by the Start Subchannel instruction is an Asynchronous Data Mover (ADM) subchannel, performing: obtaining an operation request block from main storage, the operation request block comprising an address of an operation block; based on the address of the operation block, obtaining the operation block from main storage, the operation block consisting of a request block, a response block, and one or more first move specification blocks (MSBs), wherein the request block comprises an MSB count field having a value indicating the number of one or more MSBs included in and referenced by the operation block, wherein the response block is configured to hold exception conditions, wherein each move specification block is configured to include an operation code field, a block count field, a main storage address field for addressing main storage, a storage class memory address field for addressing storage class memory, a block size field and a flags field; obtaining a move specification block of the one or more move specification blocks; determining based on the operation code in the obtained move specification block an operation that the obtained move specification block is configured to perform on blocks of storage class memory; based on the move specification block, initiating the operation on the blocks of storage class memory associated with a storage class memory address of the storage class memory address field; and responsive to at least initiating the operation and encountering an exception condition, storing information within the response block, wherein the response block comprises an exception flags field, a field validity field, a failing MSB address field, a failing indirect data address word (AIDAW) address field, a failing main storage address field and a failing storage class memory address field, the information relating to one or more exceptions resulting from the operation, wherein the one or more exceptions are related to at least one of: main storage associated with a main storage address of the main storage address field, storage class memory associated with a storage class memory address of the storage class memory address field, or the obtained move specification block, and wherein the information includes an indication of an exception and additional information relating to the exception, the additional information specifying one or more address exceptions.

    64.
    发明专利
    未知

    公开(公告)号：AT511675T

    公开(公告)日：2011-06-15

    申请号：AT09709771

    申请日：2009-02-09

    Applicant: IBM

    Inventor： CASPER DANIEL ,  CARLSON SCOTT ,  FLANAGAN JOHN ,  HATHORN ROGER ,  HUANG CATHERINE ,  KALOS MATTHEW ,  RICCI LOUIS ,  RIEDY DALE ,  SITTMANN GUSTAV III ,  UGOCHUKWU NJOKU ,  YUDENFRIEND HARRY

    IPC: G06F13/12

    Abstract: A state of an input/output (I/O) operation in an I/O processing system is determined. A request for performing the I/O operation is received from an I/O operating system at a channel subsystem and forwarded to a control unit controlling an I/O device for executing the I/O operation. After a predetermined amount of time passes without receiving indication from the control unit that the I/O operation is completed, an interrogation request is received at the channel subsystem from the I/O operating system for determining the state of the I/O operation. An interrogation command is sent from the channel subsystem to the control unit. A response is received from the control unit, the response indicates a state of the I/O device executing the I/O operation, a state of the control unit controlling the I/O device executing the I/O operation, and the state of the I/O operation being executed.

    ORDEN DE COMPUTADORA Y RESPUESTA PARA DETERMINAR EL ESTADO DE UNA OPERACION I/O.
    69.
    发明专利
    ORDEN DE COMPUTADORA Y RESPUESTA PARA DETERMINAR EL ESTADO DE UNA OPERACION I/O. 未知

    公开(公告)号：MX2010008886A

    公开(公告)日：2010-08-31

    申请号：MX2010008886

    申请日：2009-02-09

    Applicant: IBM

    Inventor： CARLSON SCOTT ,  CASPER DANIEL ,  FLANAGAN JOHN ,  KALOS MATTHEW ,  SITTMANN III GUSTAV ,  HUANG CATHERINE ,  RIEDY DALE ,  HATHORN ROGER ,  RICCI LOUIS ,  UGOCHUKWU NJOKU ,  YUDENFRIEND HARRY

    IPC: G06F13/12

    Abstract: Se determina un estado de una operación de entrada/salida (I/O) en un sistema de procesamiento I/O. Una solicitud para llevar a cabo la operación I/O se recibe de un sistema operativo I/O a un subsistema de canales y es reenviada a una unidad de control que controla un dispositivo I/O para ejecutar la operación I/O. Después de que una cantidad de tiempo predeterminada pasa sin recibir la indicación por parte de la unidad de control de que la operación I/O está completada, se recibe una petición de interrogación en el subsistema de canales del sistema operativo I/O para determinar el estado de la operación I/O. Una orden de interrogación es enviada del subsistema de canales a la unidad de control. Se recibe una respuesta de la unidad de control, la respuesta indica un estado del dispositivo I/O que ejecuta la operación I/O, un estado de la unidad de control que controla el dispositivo I/O que ejecuta la operación I/O, y el estado de la operación I/O que se está ejecutando.

    SPIEGELN VON SCHREIBOPERATIONEN ZWISCHEN DATENSPEICHEREINHEITEN
    70.
    发明专利
    SPIEGELN VON SCHREIBOPERATIONEN ZWISCHEN DATENSPEICHEREINHEITEN 未知

    公开(公告)号：DE112020002834T5

    公开(公告)日：2022-03-17

    申请号：DE112020002834

    申请日：2020-06-25

    Applicant: IBM

    Inventor： YUDENFRIEND HARRY ,  SUTTON PETER GRIMM ,  COMPTON SCOTT

    IPC: G06F16/13 ,  G06F13/42

    Abstract: Ein durch einen Computer implementiertes Verfahren gemäß einem Ansatz umfasst: Empfangen einer ersten Anforderung zum Durchführen einer Schreiboperation von einem Host und Durchführen der Schreiboperation. Metadaten, die der ersten Anforderung entsprechen, werden an die sekundäre Datenspeichereinheit gesendet, und Metadaten, die einer zweiten Anforderung zum Durchführen der Schreiboperation entsprechen, werden von der sekundären Datenspeichereinheit empfangen, wobei die zweite Anforderung vom Host in der sekundären Datenspeichereinheit empfangen wurde. Die Metadaten, die der ersten und zweiten Anforderung entsprechen, werden verwendet, um zu ermitteln, ob die Schreiboperation zwischen der primären und sekundären Datenspeichereinheit gespiegelt wurde. Als Reaktion auf ein Feststellen, dass die Schreiboperation zwischen der primären und der sekundären Datenspeichereinheit gespiegelt wurde, wird eine Antwort an die sekundäre Datenspeichereinheit gesendet, die anzeigt, dass die Schreiboperation zwischen der primären und der sekundären Datenspeichereinheit abgeglichen wurde.

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