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    INCREASING PROCESSING CAPACITY OF PARTITIONS FOR AN ABNORMAL EVENT
    3.
    发明专利
    INCREASING PROCESSING CAPACITY OF PARTITIONS FOR AN ABNORMAL EVENT 未知

    公开(公告)号：ZA202105523B

    公开(公告)日：2022-07-27

    申请号：ZA202105523

    申请日：2021-08-03

    Applicant: IBM

    Inventor： SUTTON PETER GRIMM

    Abstract: A system and related method provides within a data processing system (DPS), a first set of computing resources comprising a set of processor units that comprises a first core in an active state, and a second core that is initially in an inactive state. The processor allocates, for a partition that is hosted on the DPS, the first set of computing resources. The partition is operated using the first core before the second core has been activated. A resource manager determines whether to increase processing capacity based on an abnormal event. The processor then activates the second core from the inactive state to the active state. The partition is then operated using both the first and second (activated). In response to a predefined criterion, the second core is deactivated from the active state to the inactive state.

    INCREASING PROCESSING CAPACITY OF PARTITIONS FOR AN ABNORMAL EVENT
    4.
    发明专利
    INCREASING PROCESSING CAPACITY OF PARTITIONS FOR AN ABNORMAL EVENT 未知

    公开(公告)号：CA3128930A1

    公开(公告)日：2020-08-13

    申请号：CA3128930

    申请日：2020-01-28

    Applicant: IBM

    Inventor： SUTTON PETER GRIMM

    IPC: G06F9/50 ,  G06F1/3287 ,  G06F9/455

    Abstract: A system and related method provides within a data processing system (DPS), a first set of computing resources comprising a set of processor units that comprises a first core in an active state, and a second core that is initially in an inactive state. The processor allocates, for a partition that is hosted on the DPS, the first set of computing resources. The partition is operated using the first core before the second core has been activated. A resource manager determines whether to increase processing capacity based on an abnormal event. The processor then activates the second core from the inactive state to the active state. The partition is then operated using both the first and second (activated). In response to a predefined criterion, the second core is deactivated from the active state to the inactive state.

    Store storage class memory information command
    5.
    发明专利
    Store storage class memory information command 未知

    公开(公告)号：GB2506073A

    公开(公告)日：2014-03-19

    申请号：GB201400048

    申请日：2012-05-25

    Applicant: IBM

    Inventor： GAINEY CHARLES JR ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

    IPC: G06F13/38

    Abstract: Provided is a method of executing an instruction to execute a Store Storage Class Memory Information command in a computing environment comprising main storage and storage class memory, the method comprising: obtaining by an input/output (I/O) subsystem a request block, the request block comprising a command code indicating the Store Storage Class Memory Information command; based on the command code, obtaining by the I/O subsystem information relating to the storage class memory; and storing the information in a response block, the response block configured to include a header area and a storage class memory address list of one or more entries representing one or more storage class memory increments that occupy one or more ranges of storage class memory addresses, and wherein the storing the information comprises storing header information in the header area and storing the one or more entries in the response block, wherein the header area includes parameters about the list of one or more entries including an indication of a size of storage class memory increments.

    Increasing processing capacity of partitions for an abnormal event
    7.
    发明专利
    Increasing processing capacity of partitions for an abnormal event 未知

    公开(公告)号：AU2020219324B2

    公开(公告)日：2023-01-05

    申请号：AU2020219324

    申请日：2020-01-28

    Applicant: IBM

    Inventor： SUTTON PETER GRIMM

    IPC: G06F9/50 ,  G06F1/3287 ,  G06F9/455

    Abstract: A system and related method provides within a data processing system (DPS), a first set of computing resources comprising a set of processor units that comprises a first core in an active state, and a second core that is initially in an inactive state. The processor allocates, for a partition that is hosted on the DPS, the first set of computing resources. The partition is operated using the first core before the second core has been activated. A resource manager determines whether to increase processing capacity based on an abnormal event. The processor then activates the second core from the inactive state to the active state. The partition is then operated using both the first and second (activated). In response to a predefined criterion, the second core is deactivated from the active state to the inactive state.

    Using extended asynchronous data mover indirect data address words
    9.
    发明专利
    Using extended asynchronous data mover indirect data address words 未知

    公开(公告)号：AU2012266572B2

    公开(公告)日：2015-09-10

    申请号：AU2012266572

    申请日：2012-05-25

    Applicant: IBM

    Inventor： OAKES KENNETH JAMES ,  SUTTON PETER GRIMM ,  DRIEVER PETER DANA ,  YUDENFRIEND HARRY ,  GLASSEN STEVEN GARDNER

    IPC: G06F13/12

    Abstract: Provided is a method of executing a Start Subchannel instruction in a computing environment comprising main storage and storage class memory, said method comprising: responsive to determining that a subchannel identified by the Start Subchannel instruction is an Asynchronous Data Mover (ADM) subchannel, performing: obtaining an operation request block from main storage, the operation request block comprising an address of an operation block;based on the address of the operation block, obtaining the operation block from main storage, the operation block consisting of a request block, a response block, and one or more move specification blocks (MSBs), wherein the request block comprises an MSB count field having a value indicating the number of one or more MSBs included in and referenced by the operation block, wherein the response block is configured to hold exception conditions, wherein each move specification block is configured to include an operation code field, a block count field, a main storage address field, a storage class memory address field, a block size field and a flags field; for each MSB block of the operation block, obtaining a move specification block of the one or more move specification blocks, and: determining based on the flags field that the obtained move specification block is configured to obtain a list of one or more indirect data address words, the list of one or more indirect data address words located at a first main storage address of the main storage address field of the obtained MSB;for each block of data specified by the obtained MSB, obtaining from the list of one or more indirect data address words a second main storage address, wherein a number of blocks and a block size are determined based on the block count field and the block size field of the obtained MSB;determining based on an operation code of the operation code field in the obtained move specification block that the obtained move specification block is configured to move blocks of data; and based on the obtained move specification block, moving each block of data between the main storage and the storage class memory, wherein an address of a main storage location used for the move of a block of data is obtained using a respective second main storage address and an address of the storage class memory used for the move is obtained using the storage class memory address field.

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