公开(公告)号：DE10315049A1

公开(公告)日：2003-10-30

申请号：DE10315049

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C5/02

Abstract: The computer memory storage field (501) has first and second storage cell banks (510a,b) with zigzag edges (531,532). Blank or unused edges lie adjacent to each other. Each memory cell bank incorporates a memory block (330a,b). The system includes drivers (140a,b) for horizontal word lines (WL). Bit lines (BL) on the zigzag edges are arranged in pairs (BL-Paar) and cross each other (334) at intervals. The memory cells (331) consist of transistors.

公开(公告)号：GB2352855A

公开(公告)日：2001-02-07

申请号：GB0009818

申请日：2000-04-25

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G06F11/20

Abstract: A semiconductor integrated circuit device includes a redundant metal line 2 for replacing a non- operational metal line 4 for connecting to a circuit block 5. A spare circuit block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.