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    Network interface for data transport in heterogeneous computing environments
    61.
    发明授权
    Network interface for data transport in heterogeneous computing environments 有权

    公开(公告)号：US11025544B2

    公开(公告)日：2021-06-01

    申请号：US16435328

    申请日：2019-06-07

    Applicant: Intel Corporation

    Inventor： Pratik M. Marolia ,  Rajesh M. Sankaran ,  Ashok Raj ,  Nrupal Jani ,  Parthasarathy Sarangam ,  Robert O. Sharp

    IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

    ENFORCING UNIQUE PAGE TABLE PERMISSIONS WITH SHARED PAGE TABLES
    62.
    发明申请
    ENFORCING UNIQUE PAGE TABLE PERMISSIONS WITH SHARED PAGE TABLES 审中-公开

    公开(公告)号：US20200310665A1

    公开(公告)日：2020-10-01

    申请号：US16367944

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： David Hansen ,  Ashok Raj

    IPC: G06F3/06

    Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.

    Management of Processor Performance Based on User Interrupts
    63.
    发明申请
    Management of Processor Performance Based on User Interrupts 审中-公开

    公开(公告)号：US20200218677A1

    公开(公告)日：2020-07-09

    申请号：US16819283

    申请日：2020-03-16

    Applicant: Intel Corporation

    Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

    IPC: G06F13/24

    Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

    Management of processor performance based on user interrupts
    64.
    发明授权
    Management of processor performance based on user interrupts 有权

    公开(公告)号：US10599596B2

    公开(公告)日：2020-03-24

    申请号：US15864290

    申请日：2018-01-08

    Applicant: Intel Corporation

    Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

    IPC: G06F13/10 ,  G06F13/24 ,  G06F15/80 ,  G06F9/30

    Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

    Instruction and logic to expose error domain topology to facilitate failure isolation in a processor
    66.
    发明授权
    Instruction and logic to expose error domain topology to facilitate failure isolation in a processor 有权

    公开(公告)号：US10223187B2

    公开(公告)日：2019-03-05

    申请号：US15372734

    申请日：2016-12-08

    Applicant: INTEL CORPORATION

    Inventor： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Vincent J. Zimmer

    IPC: G06F9/30 ,  G06F11/07

    Abstract: A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.

    Instruction and logic for machine check interrupt management
    67.
    发明授权
    Instruction and logic for machine check interrupt management 有权

    公开(公告)号：US09864603B2

    公开(公告)日：2018-01-09

    申请号：US14498092

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Mohan J. Kumar

    IPC: G06F9/30

    CPC classification number: G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/3861

    Abstract: A processor includes a front end including a decoder to decode an instruction, a scheduler to assign execution of the instruction to a core, and a core to execute the instruction. The instruction specifies that interrupts such as corrected machine check interrupts are to be selectively suppressed. The processor further includes an error handling unit including logic to determine that an interrupt caused by an error is to be created and that an error consumer has requested interrupt notification. The error handling unit further includes logic to, based on the instruction specifying that interrupts are to be selectively suppressed, send the interrupt to a producer that issued the instruction rather than the error consumer.

    Context based alert system
    68.
    发明授权
    Context based alert system 有权

    公开(公告)号：US09652747B2

    公开(公告)日：2017-05-16

    申请号：US14266386

    申请日：2014-04-30

    Applicant: Intel Corporation

    Inventor： Ashok Raj

    IPC: G06Q10/10 ,  G08B21/18 ,  H04M3/436

    CPC classification number: G06Q10/1093 ,  G06Q10/103 ,  G08B21/18 ,  H04M3/436 ,  H04M2203/2072

    Abstract: An embodiment allows for context based alerts/alarms. For example, an embodiment may automatically determine that a user is in a meeting with another person based on a meeting entry in the user's calendar. In such a situation the embodiment may divert an incoming phone call, which would ordinarily result in a ring tone, to go directly to voice mail based on the calendar entry. In an embodiment the alert may be delayed until the meeting concludes. Unlike conventional systems, various embodiments do not require a user to change notification rules, manually flip a hardware switch, or create a “Do Not Disturb” setting that allows just a single “silent” time during the day. An embodiment allows data in a calendar to automatically drive the behavior of how a notification panel operates. Other embodiments are described herein.

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