公开(公告)号：US20250071924A1

公开(公告)日：2025-02-27

申请号：US18940819

申请日：2024-11-07

Applicant: Intel Corporation

Inventor： Phil Geng ,  David Shia ,  Xiang Li ,  George Vergis ,  Ralph Miele ,  Sanjoy Saha ,  Jeffory Smalley

IPC: H05K7/14

Abstract: Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.

公开(公告)号：US12144110B2

公开(公告)日：2024-11-12

申请号：US17134028

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Guixiang Tan ,  Xiang Li ,  Casey Winkel ,  George Vergis

IPC: H05K1/11 ,  H05K5/00 ,  H05K5/02 ,  H05K7/20

Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.

公开(公告)号：US11928042B2

公开(公告)日：2024-03-12

申请号：US16827974

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Dat T. Le ,  George Vergis

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/07 ,  G06F11/30 ,  G06F11/32

CPC classification number: G06F11/3058 ,  G06F1/30 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/3037 ,  G06F11/327

Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.

公开(公告)号：US11588279B2

公开(公告)日：2023-02-21

申请号：US17031800

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis

IPC: H01R13/62 ,  H01R13/66 ,  H01R12/73 ,  H01R13/635

Abstract: An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first electrical circuit component embedded in a latch of the DIMM socket. The first electrical circuit component has a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

公开(公告)号：US11500795B2

公开(公告)日：2022-11-15

申请号：US16664535

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Emily P. Chung ,  Frank T. Hady ,  George Vergis

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/32 ,  G11C7/10

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

公开(公告)号：US20210408724A1

公开(公告)日：2021-12-30

申请号：US17470646

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  Phil Geng

IPC: H01R13/627

Abstract: Systems, apparatuses and methods may provide for technology including a memory module, a motherboard, and a latch assembly coupled to the memory module and the motherboard, the latch assembly including a connector coupled to the motherboard, a first lever coupled to the connector via a first pivot point, an L-shaped load member extending through an opening in the first lever, a second lever coupled to the L-shaped load member via a second pivot point, and a spring to bias the L-shaped load member away from the opening in the first lever. The latch assembly may be used as a dual inline memory module (DIMM) retention assembly for compression mount technology (CMT) and land grid array (LGA) connector loading,

公开(公告)号：US10789010B2

公开(公告)日：2020-09-29

申请号：US15282757

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

公开(公告)号：US10467160B2

公开(公告)日：2019-11-05

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang Li ,  Yunhui Chu ,  Jun Liao ,  George Vergis ,  James A. McCall ,  Charles C. Phares ,  Konika Ganguly ,  Qin Li

IPC: G11C5/02 ,  G06F13/16 ,  G11C5/06 ,  G06F1/18 ,  H01R12/73 ,  G11C5/04 ,  G11C7/10

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US10459855B2

公开(公告)日：2019-10-29

申请号：US15201370

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Emily Chung ,  Frank T. Hady ,  George Vergis

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/10 ,  G11C16/32

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

公开(公告)号：US10342132B2

公开(公告)日：2019-07-02

申请号：US15839419

申请日：2017-12-12

Applicant: INTEL CORPORATION

Inventor： Xiang Li ,  George Vergis ,  Slobodan Mrdjan

IPC: H05K7/00 ,  H05K5/00 ,  H05K1/14 ,  H05K1/02 ,  H05K3/46 ,  H01R12/70 ,  H01R12/55 ,  H01R12/52 ,  H01R12/73

Abstract: Embodiments of the present disclosure are directed towards a memory device insertable into a PCB, e.g., a motherboard of a computing device. In some embodiments, the memory device may include a first PCB having a first thickness, to house one or more memory modules disposed on at least one side of the first PCB. The memory device may further include a layer having a second thickness, which may be attached to the side of the first PCB in an area that is proximate to an edge of the first PCB, to form a memory device portion that may be insertable into a connector slot disposed on a second PCB. The insertable portion may have a thickness that comprises the first and second thicknesses, to fit into the connector slot of the second PCB. Other embodiments may be described and/or claimed.