公开(公告)号：US09569886B2

公开(公告)日：2017-02-14

申请号：US14133757

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth ,  Aaron Lefohn

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/80 ,  G06T15/005 ,  G06T2210/52

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. An algorithm may be used to determine how the shading rate changes across the frame.

Abstract translation: 在一些实施例中，给定的帧或图片可以具有不同的着色速率。 在一个实施例中，在帧或图像的某些区域中，阴影率可以小于每像素一次，而在其它位置，每个像素可以是一次。 可以使用算法来确定阴影效率如何在整个帧上变化。

公开(公告)号：US20250166115A1

公开(公告)日：2025-05-22

申请号：US18971949

申请日：2024-12-06

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US12229871B2

公开(公告)日：2025-02-18

申请号：US17481656

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer K P ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G02B27/01 ,  G06T15/00 ,  G06T15/10 ,  G06T15/60 ,  G06V20/40 ,  G06V40/19 ,  H04N13/239 ,  H04N13/344 ,  H04N23/67 ,  H04N25/702

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US12026825B2

公开(公告)日：2024-07-02

申请号：US18306821

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Karthik Vaidyanathan

IPC: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06

CPC classification number: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06 ,  G06T2210/12

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US20240211403A1

公开(公告)日：2024-06-27

申请号：US18086441

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Karthik Vaidyanathan ,  Sreedhar Chalasani ,  Eric Liskay ,  Prathamesh Raghunath Shinde ,  Vasanth Ranganathan ,  Michael J. Norris ,  Rajasekhar Pantangi ,  Altug Koker

IPC: G06F12/0837 ,  G06F12/0811

CPC classification number: G06F12/0837 ,  G06F12/0811

Abstract: One embodiment provides a graphics processor comprising memory access circuitry configured to generate a virtual address for pixel data at a pixel coordinate on a surface in memory to facilitate the caching of the pixel data in a cache memory before the actual memory address of the pixel coordinate is able to be determined.

公开(公告)号：US11670037B2

公开(公告)日：2023-06-06

申请号：US17735902

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Karthik Vaidyanathan

IPC: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06

CPC classification number: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06 ,  G06T2210/12

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US20230148225A1

公开(公告)日：2023-05-11

申请号：US17958211

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Manu Mathew Thomas ,  Karthik Vaidyanathan ,  Anton Kaplanyan ,  SungYe Kim ,  Gabor Liktor

IPC: G06T5/00 ,  G06K9/62 ,  G06T15/06 ,  G06T3/40 ,  G06T1/20 ,  G06T5/20 ,  G06T3/00

CPC classification number: G06T5/002 ,  G06K9/6232 ,  G06T15/06 ,  G06T3/4046 ,  G06T3/4053 ,  G06T1/20 ,  G06T5/20 ,  G06T3/0093 ,  G06T2210/36

Abstract: Joint denoising and supersampling of graphics data is described. An example of a graphics processor includes multiple processing resources, including a least a first processing resource including a pipeline to perform a supersampling operation; and the pipeline including circuitry to jointly perform denoising and supersampling of received ray tracing input data, the circuitry including first circuitry to receive input data associated with an input block for a neural network, second circuitry to perform operations associated with a feature extraction and kernel prediction network of the neural network, and third circuitry to perform operations associated with a filtering block of the neural network.

公开(公告)号：US20230146259A1

公开(公告)日：2023-05-11

申请号：US17980492

申请日：2022-11-03

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Tobias Zirr

IPC: G06T3/40 ,  H04N13/271 ,  G06T3/00

CPC classification number: G06T3/4046 ,  G06T3/4053 ,  H04N13/271 ,  G06T3/0093

Abstract: Sampling across multiple views in supersampling operation is described. An example of an apparatus includes one or more processing resources configured to perform a supersampling operation for image data generated for multiple views utilizing one or more neural networks, the processing resources including at least a first circuitry to process a first current frame including first image data for a first view, and a second circuitry to process a second current frame including second image data for a second view, the first view and second view being displaced from each other, the processing resources to receive for processing the first current frame and the second current frame, and perform supersampling processing utilizing the one or more neural networks based on at least the first current frame and the second current frame and one or more prior generated frames for each of the views.

公开(公告)号：US11636567B2

公开(公告)日：2023-04-25

申请号：US17486330

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US20230066626A1

公开(公告)日：2023-03-02

申请号：US17516112

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： SungYe Kim ,  Karthik Vaidyanathan ,  Gabor Liktor ,  Manu Mathew Thomas

IPC: G06T3/40 ,  G06T3/00 ,  G06T15/50 ,  G06T19/20 ,  G06N3/04

Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling operation via a mixed precision convolutional neural network, the set of processing resources including circuitry configured to receive, at an input block of a neural network model, history data, velocity data, and current frame data, pre-process the history data, velocity data, and current frame data to generate pre-processed data, provide the pre-processed data to a feature extraction network of the neural network model, process the pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, and generate an output image via an output block of the neural network model via direct reconstruction or kernel prediction.