中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

82 records (took 0.036 seconds)

    DEVICE SECURITY MANAGER ARCHITECTURE FOR TRUSTED EXECUTION ENVIRONMENT INPUT/OUTPUT (TEE-IO) CAPABLE SYSTEM-ON-A-CHIP INTEGRATED DEVICES
    62.
    发明公开
    DEVICE SECURITY MANAGER ARCHITECTURE FOR TRUSTED EXECUTION ENVIRONMENT INPUT/OUTPUT (TEE-IO) CAPABLE SYSTEM-ON-A-CHIP INTEGRATED DEVICES 审中-公开

    公开(公告)号：US20230289433A1

    公开(公告)日：2023-09-14

    申请号：US18154334

    申请日：2023-01-13

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Jiewen Yao

    IPC: G06F21/53

    CPC classification number: G06F21/53 ,  G06F2221/033

    Abstract: Systems, methods, and apparatuses for implementing device security manager architecture for trusted execution environment input/output (TEE-IO) capable system-on-a-chip integrated devices are described. In one example, a system includes a hardware processor core configurable to implement a trust domain manager to manage one or more virtual machines as a respective trust domain isolated from a virtual machine monitor, and an input/output device coupled to the hardware processor core and comprising a device security manager circuit, wherein the device security manager circuit is to, in response to an trusted request from the trust domain manager to a control interface of the device security manager circuit, access a state of a trusted device interface of the input/output device for a trust domain of the trust domain manager, and provide a corresponding response to the trust domain manager.

    Scalable interrupt virtualization for input/output devices
    63.
    发明授权
    Scalable interrupt virtualization for input/output devices 有权

    公开(公告)号：US11734209B2

    公开(公告)日：2023-08-22

    申请号：US17550977

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Utkarsh Y. Kakaiya ,  Kun Tian

    IPC: G06F13/28 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579

    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

    Techniques for virtual machine transfer and resource management
    66.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11556363B2

    公开(公告)日：2023-01-17

    申请号：US16479395

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

    Multi-uplink device enumeration and management
    67.
    发明授权
    Multi-uplink device enumeration and management 有权

    公开(公告)号：US11550746B2

    公开(公告)日：2023-01-10

    申请号：US16727466

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Vinay Raghav ,  David J. Harriman ,  Utkarsh Y. Kakaiya

    IPC: G06F13/12 ,  G06F13/40 ,  G06F9/30 ,  G06F12/06 ,  G06F13/42

    Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.

    CRYPTOGRAPHIC COMPUTING WITH LEGACY PERIPHERAL DEVICES
    70.
    发明申请
    CRYPTOGRAPHIC COMPUTING WITH LEGACY PERIPHERAL DEVICES 有权

    公开(公告)号：US20220100911A1

    公开(公告)日：2022-03-31

    申请号：US17548170

    申请日：2021-12-10

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Abhishek Basak ,  Rupin H. Vakharwala ,  Utkarsh Y. Kakaiya

    IPC: G06F21/83 ,  G06F21/62 ,  G06F21/78

    Abstract: In one embodiment, a read request is received from a peripheral device across an interconnect, with the read request including a process identifier and an encrypted virtual address. One or more keys are obtained based on the process identifier of the read request, and the encrypted virtual address of the read request is decrypted based on the one or more keys to obtain an unencrypted virtual address. Encrypted data is retrieved from memory based on the unencrypted virtual address, and the encrypted data is decrypted based on the one or more keys to obtain plaintext data. The plaintext data is transmitted to the peripheral device across the interconnect.

Patent Agency Ranking