公开(公告)号：US11163580B2

公开(公告)日：2021-11-02

申请号：US16937132

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Altug Koker

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/06 ,  G06T1/60 ,  G06T15/00 ,  H04N19/423 ,  H04N19/436 ,  G06F9/30 ,  G06F9/50 ,  G09G5/393 ,  G06T1/20 ,  G06F8/41

Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

公开(公告)号：US20210312692A1

公开(公告)日：2021-10-07

申请号：US17173892

申请日：2021-02-11

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  David I. Standring ,  Shruti A. Sethi ,  Jeffrey S. Frizzell ,  Alan M. Curtis ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06T15/00 ,  G06F12/0813 ,  G06F13/16 ,  G06F12/084 ,  G06F12/10 ,  G06F12/02

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210312586A1

公开(公告)日：2021-10-07

申请号：US17180235

申请日：2021-02-19

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06F9/30

Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

公开(公告)号：US11120766B2

公开(公告)日：2021-09-14

申请号：US16512964

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Devan Burke ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek R. Appu

IPC: G09G5/391 ,  G09G5/38 ,  G06T1/20 ,  G09G5/36 ,  G09G5/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

公开(公告)号：US20210279836A1

公开(公告)日：2021-09-09

申请号：US17206565

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Mohammed Tameem ,  Altug Koker ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F12/02 ,  G06F12/0875

Abstract: A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

公开(公告)号：US20210279104A1

公开(公告)日：2021-09-09

申请号：US17205905

申请日：2021-03-18

Applicant: INTEL CORPORATION

Inventor： ALTUG KOKER ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu

IPC: G06F9/50 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

公开(公告)号：US11106264B2

公开(公告)日：2021-08-31

申请号：US16805480

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06T1/20 ,  G06F1/3209 ,  H04W52/02 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04M1/72448

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210263742A1

公开(公告)日：2021-08-26

申请号：US17195132

申请日：2021-03-08

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US11087522B1

公开(公告)日：2021-08-10

申请号：US16819121

申请日：2020-03-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karthik Vaidyanathan ,  Saikat Mandal ,  Michael Norris

IPC: G06T15/00 ,  G06F3/06 ,  G06T15/06

Abstract: Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

公开(公告)号：US11080213B2

公开(公告)日：2021-08-03

申请号：US16700853

申请日：2019-12-02

Applicant: INTEL CORPORATION

Inventor： Balaji Vembu ,  Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Niranjan L. Cooray

IPC: G06F13/16 ,  G06T1/60 ,  G06F9/50 ,  G06F13/40 ,  G06F12/0802 ,  G06F12/1045 ,  G06F9/48 ,  G06F12/0875

Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.