公开(公告)号：US20210279181A1

公开(公告)日：2021-09-09

申请号：US17246954

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Aditya Navale ,  Ankur Shah ,  Murali Ramadoss ,  Ben Ashbaugh ,  Ronald Silvas

IPC: G06F12/1072

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

公开(公告)号：US20210256653A1

公开(公告)日：2021-08-19

申请号：US17115555

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC: G06T1/20

Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US10997686B2

公开(公告)日：2021-05-04

申请号：US16243624

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US10922161B2

公开(公告)日：2021-02-16

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Bryan White ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Mahesh Natu

IPC: G06F11/00 ,  G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US10861126B1

公开(公告)日：2020-12-08

申请号：US16449034

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC: G06T1/20

Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US10217270B2

公开(公告)日：2019-02-26

申请号：US15445852

申请日：2017-02-28

Applicant: INTEL CORPORATION

Inventor： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter, Jr. ,  Altug Koker ,  Aditya Navale

IPC: G06T15/10 ,  G06T15/00 ,  G06T11/40

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

公开(公告)号：US20180174350A1

公开(公告)日：2018-06-21

申请号：US15386111

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Vikranth Vemulapalli ,  Chandra S. Gurram ,  Aditya Navale ,  Saurabh Sharma

IPC: G06T15/00

CPC classification number: G06T1/20 ,  G06F9/38

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.

公开(公告)号：US09817770B2

公开(公告)日：2017-11-14

申请号：US14963518

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/44 ,  G06F12/109 ,  G06F13/28 ,  G06T1/60 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

公开(公告)号：US09779473B2

公开(公告)日：2017-10-03

申请号：US15202143

申请日：2016-07-05

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06F9/48 ,  G06F12/128 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

公开(公告)号：US20170004598A1

公开(公告)日：2017-01-05

申请号：US15202143

申请日：2016-07-05

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

Abstract translation: 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。