公开(公告)号：US11594452B2

公开(公告)日：2023-02-28

申请号：US17122939

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US20220399249A1

公开(公告)日：2022-12-15

申请号：US17346895

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H05K7/20 ,  H01L25/065

Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US20220093586A1

公开(公告)日：2022-03-24

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11264493B2

公开(公告)日：2022-03-01

申请号：US15747423

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/417 ,  H01L23/15

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US10896847B2

公开(公告)日：2021-01-19

申请号：US16539957

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US10763248B2

公开(公告)日：2020-09-01

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L31/0312 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/20 ,  H01L21/36 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US10453679B2

公开(公告)日：2019-10-22

申请号：US15748619

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L25/16 ,  H01L21/02 ,  H01L21/762 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L23/48 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/18

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

公开(公告)号：US10367070B2

公开(公告)日：2019-07-30

申请号：US15754804

申请日：2015-09-24

Applicant: Intel Corporation ,  Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20180248012A1

公开(公告)日：2018-08-30

申请号：US15754804

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L29/417 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20250112187A1

公开(公告)日：2025-04-03

申请号：US18374578

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Thomas Sounart ,  YI Shi

IPC: H01L23/00 ,  H01L23/538

Abstract: A surface of an integrated circuit (IC) die structure or a host structure to which the IC die structure is to be bonded includes a biphilic surface for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. Hydrophobic regions can be self-aligned to hydrophilic regions of the biphilic surface by forming precursor metallization features within the hydrophobic regions concurrently with the formation of metallization features within the hydrophilic regions. Metallization features within the hydrophobic regions may then be at least partially removed as sacrificial to facilitate the formation of a hydrophobic surface. Metallization features within the hydrophilic regions may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.