公开(公告)号：US11244943B2

公开(公告)日：2022-02-08

申请号：US16728983

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11978784B2

公开(公告)日：2024-05-07

申请号：US17985112

申请日：2022-11-10

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/34 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/7853 ,  H01L21/02502 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11769836B2

公开(公告)日：2023-09-26

申请号：US16405807

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Tahir Ghani ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

公开(公告)号：US12206027B2

公开(公告)日：2025-01-21

申请号：US18228139

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Tahir Ghani ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

公开(公告)号：US11532734B2

公开(公告)日：2022-12-20

申请号：US16370449

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US12272688B2

公开(公告)日：2025-04-08

申请号：US17026052

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Zachary Geiger ,  Glenn A. Glass ,  Szuya S. Liao

IPC: H01L27/088 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20220093586A1

公开(公告)日：2022-03-24

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.