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公开(公告)号:US11593909B2
公开(公告)日:2023-02-28
申请号:US17475147
申请日:2021-09-14
Applicant: Intel Corporation
Inventor: Ravishankar Iyer , Selvakumar Panneer , Carl S. Marshall , John Feit , Venkat R. Gokulrangan
IPC: G06T1/20 , G06F9/48 , G06F9/50 , A63F13/358
Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.
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公开(公告)号:US20220148123A1
公开(公告)日:2022-05-12
申请号:US17475147
申请日:2021-09-14
Applicant: Intel Corporation
Inventor: Ravishankar Iyer , Selvakumar Panneer , Carl S. Marshall , John Feit , Venkat R. Gokulrangan
Abstract: An apparatus and method for scheduling threads on local and remote processing resources. For example, one embodiment of an apparatus comprises: a local graphics processor to execute threads of an application; graphics processor virtualization circuitry and/or logic to generate a virtualized representation of a local processor; a scheduler to identify a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor; the scheduler to schedule the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to Cloud-based processing resources associated with the virtualized representation of the local processor; and the local graphics processor to combine first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the Cloud-based processing resources to render an image frame.
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公开(公告)号:US10303504B2
公开(公告)日:2019-05-28
申请号:US14671515
申请日:2015-03-27
Applicant: Intel Corporation
Inventor: Matthew Fleming , Edwin Verplanke , Andrew Herdrich , Ravishankar Iyer
CPC classification number: G06F9/46 , G06F9/45558 , G06F11/30 , G06F11/301 , G06F11/3089 , G06F2009/4557 , G06F2009/45591 , G06F2201/865
Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.
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公开(公告)号:US20180285741A1
公开(公告)日:2018-10-04
申请号:US15476520
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Carl S. Marshall , Selvakumar Panneer , Ravishankar Iyer
Abstract: An embodiment of an electronic processing apparatus may include a user interface to receive an input from a user, an assistant interface to communicate with at least two electronic personal assistants, and a coordinator communicatively coupled to the user interface and the assistant interface. The coordinator may be configured to send a request to one or more of the at least two electronic personal assistants based on the input from the user, collect one or more assistant responses from the one or more electronic personal assistants, and provide a response to the user based on the collected one or more assistant responses. Other embodiments are disclosed and claimed.
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公开(公告)号:US10048743B2
公开(公告)日:2018-08-14
申请号:US15134756
申请日:2016-04-21
Applicant: Intel Corporation
Inventor: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/32 , G06F12/08 , G06F9/44 , H04W88/02 , G06F13/24 , G06F9/50 , G06F9/4401 , H04W52/02 , G06F12/084
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号:US20180089583A1
公开(公告)日:2018-03-29
申请号:US15278503
申请日:2016-09-28
Applicant: Intel Corporation
Inventor: Ravishankar Iyer , Glen J. Anderson , Omesh Tickoo , David I. Poisner , Therese E. Dugan , Mark R. Francis , Yevgeniy Y. Yarmosh
CPC classification number: G06N20/00 , G06F3/14 , G06F3/147 , G06K9/6254 , G09G2360/08 , G09G2370/16
Abstract: Systems, apparatuses and methods may provide for training smart objects. More particularly, Systems, apparatuses and methods may provide training smart objects and users to understand actions and commands, using sensors and actuators. Systems, apparatuses and methods may also provide smart objects and users a way to communicate training to other smart objects and users.
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公开(公告)号:US20180085663A1
公开(公告)日:2018-03-29
申请号:US15280192
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Blanka Vlasak , Glen J. Anderson , Meng Shi , Ravishankar Iyer , Therese E. Dugan , Mark R. Francis , David I. Poisner , Yevgeniy Y. Yarmosh
Abstract: An embodiment of an interactive play apparatus may include a camera to capture a projected image, an image recognizer communicatively coupled to the camera to recognize the captured projection image, and a projection responder communicatively coupled to the image recognizer to respond to the recognized projection image. Other embodiments are disclosed and claimed.
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公开(公告)号:US09864427B2
公开(公告)日:2018-01-09
申请号:US15134770
申请日:2016-04-21
Applicant: Intel Corporation
Inventor: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号:US09852002B2
公开(公告)日:2017-12-26
申请号:US14671515
申请日:2015-03-27
Applicant: Intel Corporation
Inventor: Matthew Fleming , Edwin Verplanke , Andrew Herdrich , Ravishankar Iyer
Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.
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公开(公告)号:US09733987B2
公开(公告)日:2017-08-15
申请号:US14627912
申请日:2015-02-20
Applicant: INTEL CORPORATION
Inventor: Andrew J. Herdrich , Kapil Sood , Nrupal R. Jani , David J. Harriman , Mesut A. Ergin , Scott P. Dubal , Ravishankar Iyer
CPC classification number: G06F9/5077
Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.
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