公开(公告)号：US20240311239A1

公开(公告)日：2024-09-19

申请号：US18679341

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F12/0804 ,  G11C11/406 ,  G11C29/42 ,  G11C29/52 ,  H03M13/09 ,  H03M13/11

CPC classification number: G06F11/1068 ,  G06F12/0804 ,  G11C29/52 ,  G06F3/0656 ,  G06F11/073 ,  G06F11/1052 ,  G06F2212/1032 ,  G06F2212/608 ,  G11C11/40607 ,  G11C29/42 ,  G11C2207/2245 ,  G11C2211/4062 ,  H03M13/098 ,  H03M13/11

Abstract: A deferred error correction code (ECC) scheme for memory devices is disclosed. A disclosed method includes starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

公开(公告)号：US20240248726A1

公开(公告)日：2024-07-25

申请号：US18628600

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G06F9/4401 ,  B60R16/023 ,  B60R16/03

CPC classification number: G06F9/4408 ,  B60R16/0231 ,  B60R16/03 ,  G06F9/4416 ,  G06F9/4418

Abstract: Disclosed are devices and methods for improving the pre-booting of electronic control unit devices in vehicles. In one embodiment, a method is disclosed comprising detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle; transmitting a power-on signal to at least one electronic control unit (ECU) in the vehicle, the at least one ECU operating in a low-power state; and fully booting the at least one ECU upon determining that the vehicle has been started.

公开(公告)号：US11789629B2

公开(公告)日：2023-10-17

申请号：US17846462

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

公开(公告)号：US11775208B2

公开(公告)日：2023-10-03

申请号：US17829861

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06 ,  G06F1/26

CPC classification number: G06F3/0656 ,  G06F1/263 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0673

Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

公开(公告)号：US11704204B2

公开(公告)日：2023-07-18

申请号：US17155641

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G06F11/18 ,  G06F12/0864 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F11/183 ,  G06F11/1004 ,  G06F11/187 ,  G06F12/0246 ,  G06F12/0864 ,  G06F2212/7201

Abstract: A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.

公开(公告)号：US11691638B2

公开(公告)日：2023-07-04

申请号：US17172946

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: B60W50/02 ,  G05D1/00

CPC classification number: B60W50/0205 ,  G05D1/0088 ,  B60W2050/021 ,  B60W2710/20 ,  B60W2720/106

Abstract: A vehicle having a control element for the speed, acceleration or direction of the vehicle, multiple identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. The commands may have one or more matching groups, where commands within each respective group agree with each other and thus vote for a candidate command representing the group. The computing device outputs a candidate command that represents the largest group for execution by the control element.

公开(公告)号：US11663104B2

公开(公告)日：2023-05-30

申请号：US17691957

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, Jr. ,  Niccolo′ Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/30 ,  G11C5/14 ,  G11C16/34

CPC classification number: G06F11/3058 ,  G06F1/30 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/3037 ,  G11C5/141 ,  G11C16/3404 ,  G11C16/3418 ,  G06F2201/84

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

公开(公告)号：US11657865B2

公开(公告)日：2023-05-23

申请号：US17149709

申请日：2021-01-14

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40615 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

公开(公告)号：US20230045250A1

公开(公告)日：2023-02-09

申请号：US17971117

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Gil Golov

IPC: G06V20/56 ,  G01C21/30 ,  G06N3/02 ,  G05D1/00 ,  G06N20/00 ,  G06F16/29 ,  G01C21/36 ,  G06V20/58

Abstract: A map in a cloud service stores physical objects previously detected by other vehicles that have previously traveled over the same road that a current vehicle is presently traveling on. New data received by the cloud service from the current vehicle regarding new objects that are being encountered by the current vehicle can be compared to the previous object data stored in the map. Based on this comparison, an operating status of the current vehicle is determined. In response to determining the status, an action such as terminating an autonomous navigation mode of the current vehicle is performed.

公开(公告)号：US11556267B2

公开(公告)日：2023-01-17

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.