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公开(公告)号：JPH07288496A
公开(公告)日：1995-10-31
申请号：JP8058094
申请日：1994-04-19
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04B7/15
Abstract: PURPOSE:To provide a repeater device which ensures the large without changing the frequency and then to obtain a simple and practical radio communication system. CONSTITUTION:A repeater station 12 is provided with a receiver antenna 14 and a transmitter antenna 16 which have the substantially same directivity and placed so that their mutual degree of coupling can be minimized. The signals received by the antenna 14 are amplified by a reception amplifier 15 and sent to a transmission power amplifier 17 via a transmission/reception connector device. The signals amplified by the amplifier 17 are transmitted through the antenna 16. It is desirable to add a directive antenna 13 to each terminal station 11 to point the station 12.
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公开(公告)号：JPH07240709A
公开(公告)日：1995-09-12
申请号：JP2874594
申请日：1994-02-28
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU , ADACHI HIROAKI
Abstract: PURPOSE:To provide the communication system where communication from a running moving body is stably performed without the loss of data due to the shadow of standing trees, utility poles, etc. CONSTITUTION:A mobile station 100 is provided with a pilot detecting circuit 8 which receives the pilot signal of a satellite and quickly detects the presence or the absence of this signal, a transmission FIFO 3 where transmission data is temporarily stored, and a transmission clock generator 6 which gives the read timing, and data quantity information stored in the FIFO 3 is received and averaged. The frequency or the transmission clock generator 6 is so controlled that the speed change proportional to the output value is brought about.
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公开(公告)号：JPH0685546A
公开(公告)日：1994-03-25
申请号：JP23231692
申请日：1992-08-31
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To miniaturize a branching filter required for bidirectional radio communication and to improve a G/T (gain noise temperature ratio) on the reception side. CONSTITUTION:On the transmission side, a first directional coupler 5 is installed at the output of a high power amplifier HPA 1 and the main output is sent through a branching filter 2 to an antenna A. This circuit is provided with a first low noise amplifier 3, a second directional coupler 9, a second low noise amplifier 4, a third directional coupler 10, a first multiplication circuit 8 to multiply the sub output of the directional coupler 10 and one part of the output from the directional coupler 5, and a DC amplifier 12 to receive the output of this multiplication circuit 8. A signal received by the antenna is supplied to the sub input of the directional coupler 9 by controlling the amplitude and phase of a signal at one part which the sub output of the directional coupler 5 is branched by a branch with the DC output of a DC amplifier 12. Then, the gain of the directional coupler 10 is enlarged by canceling a transmitting signal component leaked from the transmission side through the branching filter 2.
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公开(公告)号：JPH05122067A
公开(公告)日：1993-05-18
申请号：JP30655291
申请日：1991-10-26
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To obtain the frequency signals of fine frequency steps over a wide frequency range and also to obtain a frequency synthesizer where phase noise is suppressed. CONSTITUTION:The frequency synthesizer is constituted of a reference oscillator 1, DDS(direct-digital synthesizer) 2 generating the frequency signal which is designated by a channel number, VCO(voltage control oscillator) 8, a frequency- divider 9 frequency-dividing the output of VCO, a pulse generator 3 generating an impulse string by the output of the reference oscillator 1, a sampler 4 sampling the output of the frequency-divider 9 by the impulse string, a filter 5 smoothing the output of the sampler 4, a phase comparator 6 phase-comparing the output of the filter 5 with the output of DDS 2 and a loop filter 7 smoothing the output.
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公开(公告)号：JPH04227331A
公开(公告)日：1992-08-17
申请号：JP11885991
申请日：1991-05-23
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To realize the phase synchronization device able to surely lock an input signal quickly. CONSTITUTION:A complex multiplier 14 multiplies a 1st complex number representing an input signal with a 1st conjugation complex number representing a 1st conjugate complex signal resulting from processing and delaying the input signal to generate a 1st complex product signal. A complex multiplier 18 multiplies a phase processing signal resulting from low-pass-filtering to the 1st complex number and processing its phase with a multiplier input signal to generate a 2nd complex product signal. The 2nd complex product signal is delayed to limit the amplitude to a prescribed value and the result is given to the multiplier input signal to the complex multiplier 18. The 2nd complex product signal is processed to generate a 2nd conjugate complex signal represented in the 2nd conjugate complex number of the 2nd complex number. A complex multiplier 22 multiplies the 1st complex number with the 2nd conjugate complex number to generate a 3rd complex product signal. A 4th complex multiplier 24 multiplies the 2nd complex product signal with a 2nd filter signal resulting from low-pass-filtering to the 3rd complex product signal to generate the 4th complex product signal.
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Patent Agency Ranking
公开(公告)号：JPH043639A
公开(公告)日：1992-01-08
申请号：JP10491590
申请日：1990-04-20
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/22
Abstract: PURPOSE:To apply a demodulating circuit to a wide-ranging signal to be modulated by providing a complex multiplier and an automatic frequency control loop, which negatively feed back the output to the input side so that the frequency error of the complex multiplier is 0, between A/D converters, which digitize a quasi-synchronism detection signal, and channel filters. CONSTITUTION:A first complex multiplier 6-1 is provided between A/D converters 5-1 and 5-2 and channel filters 13-1 and 13-2, and the automatic frequency control loop which negatively feeds back the output of the complex multiplier 6-1 to the input side is added there. Since this AFC loop includes a digital integrator 9-2, the operation to completely eliminate the frequency error is performed. when the frequency error is 0, a control signal generating circuit 16 is operated as an integrator, and as the result, this loop is a phase locked loop and the frequency error is kept at 0. Thus, the same system is applied to very wide-ranging kinds of signal to be modulated.
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公开(公告)号：JPH03296327A
公开(公告)日：1991-12-27
申请号：JP9784890
申请日：1990-04-13
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To allow the system not to be made large in the circuit scale even when a mobile station is used as a reception section by using a chirp signal so as to measure the position thereby solving a problem of synchronization. CONSTITUTION:A chirp signal from a base station is multiplied with a modulated position measuring signal, the result is synthesized with an SCPC signal, the result is arranged in a prescribed frequency interval location and then sent to a transmission IF section for a communication satellite. Signals from three communication satellites are received by an antenna high frequency section, branched into three by a branching device 14 and inputted to a demodulation circuit (15-1-15-3). A correlation device 20 multiplies a received chirp signal and a local chirp signal to take the correlation of the both. A timing signal generating circuit 22 adjusts the output timing of a clock signal so that a frequency error is made zero thereby controlling a local chirp signal generating circuit 21. A position measuring signal demodulator 24 receiving the output of the correlation device 20 reproduces accurately a timing signal required for measuring the position.
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公开(公告)号：JPH03141451A
公开(公告)日：1991-06-17
申请号：JP28012489
申请日：1989-10-27
Applicant: NEC CORP , NIPPON ELECTRIC ENG
Inventor： ICHIYOSHI OSAMU , TANAKA SHINICHI , NISHIKAWA MAKOTO
IPC: G06F13/12
Abstract: PURPOSE:To select the desired ports at random by controlling an input/output latch selection means with a program contained in a digital signal processor. CONSTITUTION:A latch means 13 outputs an input port address signal 2 and an output port address signal 3 in response to a desired port selection latch and in accordance with a latch control signal 5 applied to a digital signal processor 1. Then a logic arithmetic is carried out among a gate control signal 6 applied from the processor 1 and the signals 2 and 3 applied from a latch means 13. Thus an input latch selection signal 9 and an output latch selection signal 10 are produced and applied to the input and output port via the logic circuits 11 and 12. In such a constitution, the input or output port can be selected at random.
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公开(公告)号：JPH0295291A
公开(公告)日：1990-04-06
申请号：JP24722488
申请日：1988-09-30
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To make a communication of high quality all over the earth and to instantaneously measure a position without ambiguity by arranging an even number of communication satellites on three tracks set having track surfaces orthogonally to one another. CONSTITUTION:A track 2 which has its track surface slanting at, for example, +45 deg. to the equator surface of the earth 1, a track 3 which slants at -45 deg., and a track 4 which crosses them at right angles and passes the North Pole N and South Pole S are set respectively, and four satellites 2-1-2-4, 3-1-3-4, and 4-1-4-4 each are arranged on the tracks under specific conditions. Namely, the respective communication satellites 2-1-2-4, 3-1-3-4, and 4-1-4-4 are so arranged on the corresponding tracks so that the satellites revolve around the earth at intervals of, for example, one day and points (intersections) where the tracks are seen crossing one another at equal time intervals in order. Consequently, at least one communication satellite can be acquired at a >=40 deg. elevation angle all over the earth and the communication of high quality is enabled. Further, a position is measured all over the earth without ambiguity.
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公开(公告)号：JPH01269331A
公开(公告)日：1989-10-26
申请号：JP9856188
申请日：1988-04-21
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L7/00
Abstract: PURPOSE:To easily realize speed ratio very close to '1' by providing digitally controlled oscillators at an input side and an output side respectively, and driving these oscillators by common high speed clock. CONSTITUTION:The digitally controlled oscillator 2a and the same 2b are provided respectively at the input side and the output side of a signal processing circuit 1, and the high speed clock is supplied to these from a high speed clock generator 3a. The digitally controlled oscillators 2a, 2b are constituted of digital integration circuits consisting of delaying units 4 to perform the delay operation of one step and adders 5 which perform the binary addition of the output of the delaying unit 4 and a control value (m or n) to be given from an external part and output the result and simultaneously, feedback-output it to the delaying unit 4. Thus, by setting properly the control value (k), the clock of the frequency of the optional integer times of DELTAf can be generated, and in addition, by increasing the number of stages L of the adders 5, DELTAf can be made small to any extent. Namely, the speed ratio close to '1' without limit can be easily realized.
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